int actual_dispclk_set_mhz = -1;
        struct dc *core_dc = clk_mgr->base.ctx->dc;
        struct dmcu *dmcu = core_dc->res_pool->dmcu;
-       uint32_t clk = requested_dispclk_khz / 1000;
-
-       if (clk <= 100)
-               clk = 101;
 
        /*  Unit of SMU msg parameter is Mhz */
        actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
                        clk_mgr,
                        VBIOSSMC_MSG_SetDispclkFreq,
-                       clk);
+                       requested_dispclk_khz / 1000);
 
        if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
                if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 {
        int actual_dppclk_set_mhz = -1;
 
-       uint32_t clk = requested_dpp_khz / 1000;
-
-       if (clk <= 100)
-               clk = 101;
-
        actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
                        clk_mgr,
                        VBIOSSMC_MSG_SetDppclkFreq,
-                       clk);
+                       requested_dpp_khz / 1000);
 
        return actual_dppclk_set_mhz * 1000;
 }