drm/xe: Drop GFX_FLSH_CNTL_GEN6 write during GGTT invalidation

The write of GFX_FLSH_CNTL_GEN6 was inherited from the i915 codebase
where it was used to force a flush of the write-combine buffer in cases
where the GSM/GGTT were mapped as WC.  Since Xe never uses WC mappings
of the GGTT, this register write is unnecessary.  Furthermore, this
register was removed on Xe_HP-based platforms, so this write winds up
clobbering an unrelated register.

v2:
 - Also drop GFX_FLSH_CNTL_GEN6 from the register file now that it's no
   longer used.  (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230418230247.3802438-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 8fc7677e2d13e52c45260ced172032096f098be5..c1d73f3e7bc35ef389f16b24b2e6929ae8a103a8 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -351,9 +351,6 @@
 #define GEN6_GT_GFX_RC6_LOCKED                 _MMIO(0x138104)
 #define GEN6_GT_GFX_RC6                                _MMIO(0x138108)
 
-#define GFX_FLSH_CNTL_GEN6                     _MMIO(0x101008)
-#define   GFX_FLSH_CNTL_EN                     (1 << 0)
-
 #define GT_INTR_DW(x)                          _MMIO(0x190018 + ((x) * 4))
 
 #define GUC_SG_INTR_ENABLE                     _MMIO(0x190038)

diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 99bc9036c7a0d3a82965c1ab03e296a6498e29a3..0fda9a18049b0ac58f5b658ec7f30d284d0e05af 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -196,11 +196,6 @@ void xe_ggtt_invalidate(struct xe_gt *gt)
 {
        /* TODO: vfunc for GuC vs. non-GuC */
 
-       /* TODO: i915 makes comments about this being uncached and
-        * therefore flushing WC buffers.  Is that really true here?
-        */
-       xe_mmio_write32(gt, GFX_FLSH_CNTL_GEN6.reg, GFX_FLSH_CNTL_EN);
-
        if (gt->uc.guc.submission_state.enabled) {
                int seqno;