clk: renesas: r8a779h0: Add EtherAVB clocks
authorCong Dang <cong.dang.xn@renesas.com>
Sun, 11 Feb 2024 14:22:46 +0000 (15:22 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 20 Feb 2024 10:32:35 +0000 (11:32 +0100)
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a5b4252d9822ded3fd523bc35417306cae2ec2bd.1707661303.git.geert+renesas@glider.be
drivers/clk/renesas/r8a779h0-cpg-mssr.c

index 70d104393594091c3c26367bb5e766258253177c..46202e367d713d41d3dc2af7acc24f1aa6be9836 100644 (file)
@@ -173,6 +173,9 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
 };
 
 static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
+       DEF_MOD("avb0:rgmii0",  211,    R8A779H0_CLK_S0D8_HSC),
+       DEF_MOD("avb1:rgmii1",  212,    R8A779H0_CLK_S0D8_HSC),
+       DEF_MOD("avb2:rgmii2",  213,    R8A779H0_CLK_S0D8_HSC),
        DEF_MOD("hscif0",       514,    R8A779H0_CLK_SASYNCPERD1),
        DEF_MOD("hscif1",       515,    R8A779H0_CLK_SASYNCPERD1),
        DEF_MOD("hscif2",       516,    R8A779H0_CLK_SASYNCPERD1),