drm/xe: Drop WA 16015675438

With dynamic load-balancing disabled on the compute side, there's no
reason left to enable WA 16015675438. Drop it from both PVC and DG2.

Note that this can be done because now the driver always set a fixed
partition of EUs during initialization via the ccs_mode configuration.

Cc: Mateusz Jablonski <mateusz.jablonski@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Acked-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240304233103.1687412-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 0d2a2dd13f112115ae3e754fb2c28de6affc87ed..caa86ccbe9e75eeeee14a711b958453f95bb86d7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -164,7 +164,7 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
        if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685))
                flags |= GUC_WA_CONTEXT_ISOLATION;
 
-       if ((XE_WA(gt, 16015675438) || XE_WA(gt, 18020744125)) &&
+       if (XE_WA(gt, 18020744125) &&
            !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))
                flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
 

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index bcc285f45a1ebfb4e4792d08f5a6025c29178055..2460c570e6287032a7ba2f3277a4192b8d21d3b7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -328,12 +328,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
        },
-       { XE_RTP_NAME("16015675438"),
-         XE_RTP_RULES(PLATFORM(DG2),
-                      FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),
-                            PERF_FIX_BALANCING_CFE_DISABLE))
-       },
        { XE_RTP_NAME("18028616096"),
          XE_RTP_RULES(PLATFORM(DG2),
                       FUNC(xe_rtp_match_first_render_or_compute)),
@@ -383,11 +377,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
        },
-       { XE_RTP_NAME("16015675438"),
-         XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),
-                            PERF_FIX_BALANCING_CFE_DISABLE))
-       },
        { XE_RTP_NAME("14014999345"),
          XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
                       GRAPHICS_STEP(B0, C0)),

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index b138cbd51bdb1fdf7194c513cb69724a6a5b1c5b..48cdba1cbf95e93453442a28c5764688c308c5a3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -4,9 +4,6 @@
 22011391025    PLATFORM(DG2)
 22012727170    SUBPLATFORM(DG2, G11)
 22012727685    SUBPLATFORM(DG2, G11)
-16015675438    PLATFORM(PVC)
-               SUBPLATFORM(DG2, G10)
-               SUBPLATFORM(DG2, G12)
 18020744125    PLATFORM(PVC)
 1509372804     PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
 1409600907     GRAPHICS_VERSION_RANGE(1200, 1250)