arm64/sysreg: Add new system registers for GCS

FEAT_GCS introduces a number of new system registers. Add the registers
available up to EL2 to sysreg as per DDI0601 2022-12.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Fuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-13-45284e538474@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 2698dcd4976545e2c845ee0b3b41d6555194fad3..2c4b6665c5bf185e0a3238c0cf734bf6312a8958 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1903,6 +1903,41 @@ Sysreg   SMCR_EL1        3       0       1       2       6
 Fields SMCR_ELx
 EndSysreg
 
+SysregFields   GCSCR_ELx
+Res0   63:10
+Field  9       STREn
+Field  8       PUSHMEn
+Res0   7
+Field  6       EXLOCKEN
+Field  5       RVCHKEN
+Res0   4:1
+Field  0       PCRSEL
+EndSysregFields
+
+Sysreg GCSCR_EL1       3       0       2       5       0
+Fields GCSCR_ELx
+EndSysreg
+
+SysregFields   GCSPR_ELx
+Field  63:3    PTR
+Res0   2:0
+EndSysregFields
+
+Sysreg GCSPR_EL1       3       0       2       5       1
+Fields GCSPR_ELx
+EndSysreg
+
+Sysreg GCSCRE0_EL1     3       0       2       5       2
+Res0   63:11
+Field  10      nTR
+Field  9       STREn
+Field  8       PUSHMEn
+Res0   7:6
+Field  5       RVCHKEN
+Res0   4:1
+Field  0       PCRSEL
+EndSysreg
+
 Sysreg ALLINT  3       0       4       3       0
 Res0   63:14
 Field  13      ALLINT
@@ -2133,6 +2168,10 @@ Field    4       DZP
 Field  3:0     BS
 EndSysreg
 
+Sysreg GCSPR_EL0       3       3       2       5       1
+Fields GCSPR_ELx
+EndSysreg
+
 Sysreg SVCR    3       3       4       2       2
 Res0   63:2
 Field  1       ZA
@@ -2531,6 +2570,14 @@ Sysreg   SMCR_EL2        3       4       1       2       6
 Fields SMCR_ELx
 EndSysreg
 
+Sysreg GCSCR_EL2       3       4       2       5       0
+Fields GCSCR_ELx
+EndSysreg
+
+Sysreg GCSPR_EL2       3       4       2       5       1
+Fields GCSPR_ELx
+EndSysreg
+
 Sysreg DACR32_EL2      3       4       3       0       0
 Res0   63:32
 Field  31:30   D15
@@ -2590,6 +2637,14 @@ Sysreg   SMCR_EL12       3       5       1       2       6
 Fields SMCR_ELx
 EndSysreg
 
+Sysreg GCSCR_EL12      3       5       2       5       0
+Fields GCSCR_ELx
+EndSysreg
+
+Sysreg GCSPR_EL12      3       5       2       5       1
+Fields GCSPR_ELx
+EndSysreg
+
 Sysreg FAR_EL12        3       5       6       0       0
 Field  63:0    ADDR
 EndSysreg