rtw89: 8852c: process logic efuse map
authorPing-Ke Shih <pkshih@realtek.com>
Mon, 7 Mar 2022 06:04:57 +0000 (14:04 +0800)
committerKalle Valo <kvalo@kernel.org>
Thu, 10 Mar 2022 16:44:02 +0000 (18:44 +0200)
Add a struct to access logic efuse map, and fill data according to the map.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220307060457.56789-14-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8852c.h

index df6e9bf69f90a2ffaa7b8d0a6e95ef974059559a..35a9f40af3c99ac9bef7fd8fc45a41837074c015 100644 (file)
@@ -221,6 +221,72 @@ static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
        return 0;
 }
 
+static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse,
+                                    struct rtw8852c_efuse *map)
+{
+       ether_addr_copy(efuse->addr, map->e.mac_addr);
+       efuse->rfe_type = map->rfe_type;
+       efuse->xtal_cap = map->xtal_k;
+}
+
+static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
+                                       struct rtw8852c_efuse *map)
+{
+       struct rtw89_tssi_info *tssi = &rtwdev->tssi;
+       struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
+       u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
+       u8 i, j;
+
+       tssi->thermal[RF_PATH_A] = map->path_a_therm;
+       tssi->thermal[RF_PATH_B] = map->path_b_therm;
+
+       for (i = 0; i < RF_PATH_NUM_8852C; i++) {
+               memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
+                      sizeof(ofst[i]->cck_tssi));
+
+               for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
+                       rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+                                   "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
+                                   i, j, tssi->tssi_cck[i][j]);
+
+               memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
+                      sizeof(ofst[i]->bw40_tssi));
+               memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
+                      ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
+               memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
+                      sizeof(tssi->tssi_6g_mcs[i]));
+
+               for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
+                       rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+                                   "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
+                                   i, j, tssi->tssi_mcs[i][j]);
+       }
+}
+
+static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
+{
+       struct rtw89_efuse *efuse = &rtwdev->efuse;
+       struct rtw8852c_efuse *map;
+
+       map = (struct rtw8852c_efuse *)log_map;
+
+       efuse->country_code[0] = map->country_code[0];
+       efuse->country_code[1] = map->country_code[1];
+       rtw8852c_efuse_parsing_tssi(rtwdev, map);
+
+       switch (rtwdev->hci.type) {
+       case RTW89_HCI_TYPE_PCIE:
+               rtw8852c_e_efuse_parsing(efuse, map);
+               break;
+       default:
+               return -ENOTSUPP;
+       }
+
+       rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
+
+       return 0;
+}
+
 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
 {
        struct rtw89_tssi_info *tssi = &rtwdev->tssi;
@@ -376,6 +442,7 @@ static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
 }
 
 static const struct rtw89_chip_ops rtw8852c_chip_ops = {
+       .read_efuse             = rtw8852c_read_efuse,
        .read_phycap            = rtw8852c_read_phycap,
        .power_trim             = rtw8852c_power_trim,
        .pwr_on_func            = rtw8852c_pwr_on_func,
index 8abca49e6c84b87ffefe7b45b0cae4f2ae899383..d0594716040bcc3ed3db598dc91445a7a7bbca89 100644 (file)
@@ -9,6 +9,68 @@
 
 #define RF_PATH_NUM_8852C 2
 
+struct rtw8852c_u_efuse {
+       u8 rsvd[0x38];
+       u8 mac_addr[ETH_ALEN];
+};
+
+struct rtw8852c_e_efuse {
+       u8 mac_addr[ETH_ALEN];
+};
+
+struct rtw8852c_tssi_offset {
+       u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
+       u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
+       u8 rsvd[7];
+       u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
+} __packed;
+
+struct rtw8852c_efuse {
+       u8 rsvd[0x210];
+       struct rtw8852c_tssi_offset path_a_tssi;
+       u8 rsvd1[10];
+       struct rtw8852c_tssi_offset path_b_tssi;
+       u8 rsvd2[94];
+       u8 channel_plan;
+       u8 xtal_k;
+       u8 rsvd3;
+       u8 iqk_lck;
+       u8 rsvd4[5];
+       u8 reg_setting:2;
+       u8 tx_diversity:1;
+       u8 rx_diversity:2;
+       u8 ac_mode:1;
+       u8 module_type:2;
+       u8 rsvd5;
+       u8 shared_ant:1;
+       u8 coex_type:3;
+       u8 ant_iso:1;
+       u8 radio_on_off:1;
+       u8 rsvd6:2;
+       u8 eeprom_version;
+       u8 customer_id;
+       u8 tx_bb_swing_2g;
+       u8 tx_bb_swing_5g;
+       u8 tx_cali_pwr_trk_mode;
+       u8 trx_path_selection;
+       u8 rfe_type;
+       u8 country_code[2];
+       u8 rsvd7[3];
+       u8 path_a_therm;
+       u8 path_b_therm;
+       u8 rsvd8[46];
+       u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM];
+       u8 rsvd9[10];
+       u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM];
+       u8 rsvd10[110];
+       u8 channel_plan_6g;
+       u8 rsvd11[71];
+       union {
+               struct rtw8852c_u_efuse u;
+               struct rtw8852c_e_efuse e;
+       };
+} __packed;
+
 extern const struct rtw89_chip_info rtw8852c_chip_info;
 
 #endif