drm/amd/display: Enable RCO options for dcn35

[Why & How]
Enable root clock optimization options for dcn35
for power savings

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
index addedcfd1238beb4eeec681e20b7a41c91b5f40f..277aae811eea8129773867fdf4268774e1c6a164 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
@@ -754,6 +754,7 @@ static const struct dccg_funcs dccg35_funcs = {
        .disable_symclk32_se = dccg31_disable_symclk32_se,
        .enable_symclk32_le = dccg31_enable_symclk32_le,
        .disable_symclk32_le = dccg31_disable_symclk32_le,
+       .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,
        .set_physymclk = dccg35_set_physymclk,
        .set_dtbclk_dto = dccg35_set_dtbclk_dto,
        .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 3c7c810bab1ff79b26fffb2ed710c512f5ce302b..9699adf52e156c71b1b866d78dc26aa7771e1b43 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -719,14 +719,14 @@ static const struct dc_debug_options debug_defaults_drv = {
                .bits = {
                        .dpp = true,
                        .dsc = true,/*dscclk and dsc pg*/
-                       .hdmistream = false,
-                       .hdmichar = false,
-                       .dpstream = false,
-                       .symclk32_se = false,
-                       .symclk32_le = false,
-                       .symclk_fe = false,
-                       .physymclk = false,
-                       .dpiasymclk = false,
+                       .hdmistream = true,
+                       .hdmichar = true,
+                       .dpstream = true,
+                       .symclk32_se = true,
+                       .symclk32_le = true,
+                       .symclk_fe = true,
+                       .physymclk = false, // Prevents eDP light up
+                       .dpiasymclk = true,
                }
        },
        .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,