return 0;
}
-DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
+static void pxa2xx_pic_reset_hold(Object *obj)
{
- DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
- PXA2xxPICState *s = PXA2XX_PIC(dev);
-
- s->cpu = cpu;
+ PXA2xxPICState *s = PXA2XX_PIC(obj);
s->int_pending[0] = 0;
s->int_pending[1] = 0;
s->int_enabled[1] = 0;
s->is_fiq[0] = 0;
s->is_fiq[1] = 0;
+}
+
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
+{
+ DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
+ PXA2xxPICState *s = PXA2XX_PIC(dev);
+
+ s->cpu = cpu;
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "PXA2xx PIC";
dc->vmsd = &vmstate_pxa2xx_pic_regs;
+ rc->phases.hold = pxa2xx_pic_reset_hold;
}
static const TypeInfo pxa2xx_pic_info = {