arm64: dts: mt8173: Add gce setting in mmsys and display node

In order to use GCE function, we need add some informations
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index ccb8e88a60c5a5b2512558a876f1c1b1c20558b5..8337ba42845d6043e0fbece1a80d0053eb8ae34b 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -549,7 +549,7 @@
                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
                        clocks = <&infracfg CLK_INFRA_GCE>;
                        clock-names = "gce";
-                       #mbox-cells = <3>;
+                       #mbox-cells = <2>;
                };
 
                mipi_tx0: mipi-dphy@10215000 {
@@ -916,6 +916,9 @@
                        assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
                        assigned-clock-rates = <400000000>;
                        #clock-cells = <1>;
+                       mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+                                <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
                };
 
                mdp_rdma0: rdma@14001000 {
@@ -996,6 +999,7 @@
                        clocks = <&mmsys CLK_MM_DISP_OVL0>;
                        iommus = <&iommu M4U_PORT_DISP_OVL0>;
                        mediatek,larb = <&larb0>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
                };
 
                ovl1: ovl@1400d000 {
@@ -1006,6 +1010,7 @@
                        clocks = <&mmsys CLK_MM_DISP_OVL1>;
                        iommus = <&iommu M4U_PORT_DISP_OVL1>;
                        mediatek,larb = <&larb4>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
                };
 
                rdma0: rdma@1400e000 {
@@ -1016,6 +1021,7 @@
                        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
                        mediatek,larb = <&larb0>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
                };
 
                rdma1: rdma@1400f000 {
@@ -1026,6 +1032,7 @@
                        clocks = <&mmsys CLK_MM_DISP_RDMA1>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA1>;
                        mediatek,larb = <&larb4>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
                };
 
                rdma2: rdma@14010000 {
@@ -1036,6 +1043,7 @@
                        clocks = <&mmsys CLK_MM_DISP_RDMA2>;
                        iommus = <&iommu M4U_PORT_DISP_RDMA2>;
                        mediatek,larb = <&larb4>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
                };
 
                wdma0: wdma@14011000 {
@@ -1046,6 +1054,7 @@
                        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
                        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
                        mediatek,larb = <&larb0>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
                };
 
                wdma1: wdma@14012000 {
@@ -1056,6 +1065,7 @@
                        clocks = <&mmsys CLK_MM_DISP_WDMA1>;
                        iommus = <&iommu M4U_PORT_DISP_WDMA1>;
                        mediatek,larb = <&larb4>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
                };
 
                color0: color@14013000 {
@@ -1064,6 +1074,7 @@
                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
                };
 
                color1: color@14014000 {
@@ -1072,6 +1083,7 @@
                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_COLOR1>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
                };
 
                aal@14015000 {
@@ -1080,6 +1092,7 @@
                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_AAL>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
                };
 
                gamma@14016000 {
@@ -1088,6 +1101,7 @@
                        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
                };
 
                merge@14017000 {
@@ -1193,6 +1207,8 @@
                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
                        clocks = <&mmsys CLK_MM_MUTEX_32K>;
+                       mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+                                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
                };
 
                larb0: larb@14021000 {