arm64: dts: ti: k3-j721s2-main: Add the main domain watchdog instances

There are totally 9 instances of watchdog module. One each for the
2 A72 cores, one each for the 2 C7x cores, 1 for the GPU, 1 each
for the 4 R5F cores in the main domain. Keeping only the A72 instances
enabled and reserving the rest by default as they will be used by
their respective firmware.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20231008044657.25788-7-j-keerthy@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1ff1445f9d849c2d549939fab49f6dd717bb8250..b03731b53a26313b07d9163e4c8bdf6e8a9c162a 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1825,4 +1825,104 @@
                ti,esm-pins = <688>, <689>;
                bootph-pre-ram;
        };
+
+       watchdog0: watchdog@2200000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2200000 0x00 0x100>;
+               clocks = <&k3_clks 286 1>;
+               power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 286 1>;
+               assigned-clock-parents = <&k3_clks 286 5>;
+       };
+
+       watchdog1: watchdog@2210000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2210000 0x00 0x100>;
+               clocks = <&k3_clks 287 1>;
+               power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 287 1>;
+               assigned-clock-parents = <&k3_clks 287 5>;
+       };
+
+       /*
+        * The following RTI instances are coupled with MCU R5Fs, c7x and
+        * GPU so keeping them reserved as these will be used by their
+        * respective firmware
+        */
+       watchdog2: watchdog@22f0000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x22f0000 0x00 0x100>;
+               clocks = <&k3_clks 290 1>;
+               power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 290 1>;
+               assigned-clock-parents = <&k3_clks 290 5>;
+               /* reserved for GPU */
+               status = "reserved";
+       };
+
+       watchdog3: watchdog@2300000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2300000 0x00 0x100>;
+               clocks = <&k3_clks 288 1>;
+               power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 288 1>;
+               assigned-clock-parents = <&k3_clks 288 5>;
+               /* reserved for C7X_0 */
+               status = "reserved";
+       };
+
+       watchdog4: watchdog@2310000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2310000 0x00 0x100>;
+               clocks = <&k3_clks 289 1>;
+               power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 289 1>;
+               assigned-clock-parents = <&k3_clks 289 5>;
+               /* reserved for C7X_1 */
+               status = "reserved";
+       };
+
+       watchdog5: watchdog@23c0000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x23c0000 0x00 0x100>;
+               clocks = <&k3_clks 291 1>;
+               power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 291 1>;
+               assigned-clock-parents = <&k3_clks 291 5>;
+               /* reserved for MAIN_R5F0_0 */
+               status = "reserved";
+       };
+
+       watchdog6: watchdog@23d0000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x23d0000 0x00 0x100>;
+               clocks = <&k3_clks 292 1>;
+               power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 292 1>;
+               assigned-clock-parents = <&k3_clks 292 5>;
+               /* reserved for MAIN_R5F0_1 */
+               status = "reserved";
+       };
+
+       watchdog7: watchdog@23e0000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x23e0000 0x00 0x100>;
+               clocks = <&k3_clks 293 1>;
+               power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 293 1>;
+               assigned-clock-parents = <&k3_clks 293 5>;
+               /* reserved for MAIN_R5F1_0 */
+               status = "reserved";
+       };
+
+       watchdog8: watchdog@23f0000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x23f0000 0x00 0x100>;
+               clocks = <&k3_clks 294 1>;
+               power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 294 1>;
+               assigned-clock-parents = <&k3_clks 294 5>;
+               /* reserved for MAIN_R5F1_1 */
+               status = "reserved";
+       };
 };