arm64: dts: lx2160a-qds: Add mdio mux nodes

The two external MDIO buses used to communicate with phy devices that
are external to SOC are muxed in LX2160AQDS board.  These buses can be
routed to any one of the eight IO slots on LX2160AQDS board depending on
value in fpga register 0x54.  Additionally the external MDIO1 is used to
communicate to the onboard RGMII phy devices.  The mdio1 is controlled
by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga
register.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 8354af0b31e36169c43778762557c7e75c5fd6e5..2ecfa90f5e28e16cf107e88b026a8ff4978fc9ce 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -31,6 +31,130 @@
                regulator-boot-on;
                regulator-always-on;
        };
+
+       mdio-mux-1 {
+               compatible = "mdio-mux-multiplexer";
+               mux-controls = <&mux 0>;
+               mdio-parent-bus = <&emdio1>;
+               #address-cells=<1>;
+               #size-cells = <0>;
+
+               mdio@0 { /* On-board PHY #1 RGMI1*/
+                       reg = <0x00>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@8 { /* On-board PHY #2 RGMI2*/
+                       reg = <0x8>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@18 { /* Slot #1 */
+                       reg = <0x18>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@19 { /* Slot #2 */
+                       reg = <0x19>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1a { /* Slot #3 */
+                       reg = <0x1a>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1b { /* Slot #4 */
+                       reg = <0x1b>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1c { /* Slot #5 */
+                       reg = <0x1c>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1d { /* Slot #6 */
+                       reg = <0x1d>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1e { /* Slot #7 */
+                       reg = <0x1e>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1f { /* Slot #8 */
+                       reg = <0x1f>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
+       mdio-mux-2 {
+               compatible = "mdio-mux-multiplexer";
+               mux-controls = <&mux 1>;
+               mdio-parent-bus = <&emdio2>;
+               #address-cells=<1>;
+               #size-cells = <0>;
+
+               mdio@0 { /* Slot #1 (secondary EMI) */
+                       reg = <0x00>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@1 { /* Slot #2 (secondary EMI) */
+                       reg = <0x01>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@2 { /* Slot #3 (secondary EMI) */
+                       reg = <0x02>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@3 { /* Slot #4 (secondary EMI) */
+                       reg = <0x03>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@4 { /* Slot #5 (secondary EMI) */
+                       reg = <0x04>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@5 { /* Slot #6 (secondary EMI) */
+                       reg = <0x05>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@6 { /* Slot #7 (secondary EMI) */
+                       reg = <0x06>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               mdio@7 { /* Slot #8 (secondary EMI) */
+                       reg = <0x07>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
 };
 
 &can0 {
@@ -81,6 +205,14 @@
        };
 };
 
+&emdio1 {
+       status = "okay";
+};
+
+&emdio2 {
+       status = "okay";
+};
+
 &esdhc0 {
        status = "okay";
 };
@@ -107,6 +239,19 @@
 &i2c0 {
        status = "okay";
 
+       fpga@66 {
+               compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
+                            "simple-mfd";
+               reg = <0x66>;
+
+               mux: mux-controller {
+                       compatible = "reg-mux";
+                       #mux-control-cells = <1>;
+                       mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+                                       <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
+               };
+       };
+
        i2c-mux@77 {
                compatible = "nxp,pca9547";
                reg = <0x77>;