arm64: dts: renesas: r9a07g044: Add WDT nodes

Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 71f1701a1b66234e8cc3da9e5687a2c32b192c2d..82d9c620a4dec81be78a49fd327808e275c5a22f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -792,6 +792,51 @@
                        status = "disabled";
                };
 
+               wdt0: watchdog@12800800 {
+                       compatible = "renesas,r9a07g044-wdt",
+                                    "renesas,rzg2l-wdt";
+                       reg = <0 0x12800800 0 0x400>;
+                       clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
+                                <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
+                       clock-names = "pclk", "oscclk";
+                       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "wdt", "perrout";
+                       resets = <&cpg R9A07G044_WDT0_PRESETN>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt1: watchdog@12800c00 {
+                       compatible = "renesas,r9a07g044-wdt",
+                                    "renesas,rzg2l-wdt";
+                       reg = <0 0x12800C00 0 0x400>;
+                       clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
+                                <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
+                       clock-names = "pclk", "oscclk";
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "wdt", "perrout";
+                       resets = <&cpg R9A07G044_WDT1_PRESETN>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt2: watchdog@12800400 {
+                       compatible = "renesas,r9a07g044-wdt",
+                                    "renesas,rzg2l-wdt";
+                       reg = <0 0x12800400 0 0x400>;
+                       clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
+                                <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
+                       clock-names = "pclk", "oscclk";
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "wdt", "perrout";
+                       resets = <&cpg R9A07G044_WDT2_PRESETN>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                ostm0: timer@12801000 {
                        compatible = "renesas,r9a07g044-ostm",
                                     "renesas,ostm";