drm/nouveau/mc: move NV_PMC_ENABLE bashing to chipset-specific code
authorBen Skeggs <bskeggs@redhat.com>
Wed, 1 Jun 2022 10:46:55 +0000 (20:46 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 9 Nov 2022 00:44:36 +0000 (10:44 +1000)
Ampere needs different handling here, most of what we touch has moved.

We probably want to refactor these interfaces in general, but I'm not
yet sure how they should look, this will get the job done for now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
16 files changed:
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h

index 322237e2ff80e8af396d83d720ca49d32e46eed3..c85600ba69f9d06fe6c2e66498dd0e369c4417bd 100644 (file)
@@ -73,9 +73,8 @@ nvkm_mc_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
 {
        u64 pmc_enable = nvkm_mc_reset_mask(device, true, type, inst);
        if (pmc_enable) {
-               nvkm_mask(device, 0x000200, pmc_enable, 0x00000000);
-               nvkm_mask(device, 0x000200, pmc_enable, pmc_enable);
-               nvkm_rd32(device, 0x000200);
+               device->mc->func->device->disable(device->mc, pmc_enable);
+               device->mc->func->device->enable(device->mc, pmc_enable);
        }
 }
 
@@ -84,17 +83,15 @@ nvkm_mc_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst
 {
        u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
        if (pmc_enable)
-               nvkm_mask(device, 0x000200, pmc_enable, 0x00000000);
+               device->mc->func->device->disable(device->mc, pmc_enable);
 }
 
 void
 nvkm_mc_enable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
 {
        u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
-       if (pmc_enable) {
-               nvkm_mask(device, 0x000200, pmc_enable, pmc_enable);
-               nvkm_rd32(device, 0x000200);
-       }
+       if (pmc_enable)
+               device->mc->func->device->enable(device->mc, pmc_enable);
 }
 
 bool
@@ -102,11 +99,9 @@ nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_subdev_type type, int inst
 {
        u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
 
-       return (pmc_enable != 0) &&
-              ((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable);
+       return (pmc_enable != 0) && device->mc->func->device->enabled(device->mc, pmc_enable);
 }
 
-
 static int
 nvkm_mc_init(struct nvkm_subdev *subdev)
 {
index 8a8267ecfe1d89533ba9b9266a4eb537ff13f203..9feb7d167d2362e55135660cf135bb37bfc8a1aa 100644 (file)
@@ -56,6 +56,7 @@ g84_mc = {
        .init = nv50_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = g84_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = g84_mc_reset,
 };
 
index e099d419f1ce5689e47929c77bb7df1d131ae342..b0b328044e55a7a3f71dd76be0f889a2cca3c8c1 100644 (file)
@@ -56,6 +56,7 @@ g98_mc = {
        .init = nv50_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = g98_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = g98_mc_reset,
 };
 
index 98ccce9585ebcc454d4b1aa4e71de3f09c458b4e..842326a243935ede319bad5abb08ac9c62527d81 100644 (file)
@@ -24,6 +24,7 @@
 static const struct nvkm_mc_func
 ga100_mc = {
        .init = nv50_mc_init,
+       .device = &nv04_mc_device,
        .reset = gk104_mc_reset,
 };
 
index b2846eaea34c48597e6edd9537c7992ea4b60f95..d5dba44235cf3647a15e798e4db9aa65075eebab 100644 (file)
@@ -71,6 +71,7 @@ gf100_mc = {
        .intrs = gf100_mc_intrs,
        .intr_nonstall = true,
        .reset = gf100_mc_reset,
+       .device = &nv04_mc_device,
        .unk260 = gf100_mc_unk260,
 };
 
index edf82e4568bf9070cc07f55f86db0aa25bef3dcf..023dfda735cda7e31fbe596327d078f46d95b9d3 100644 (file)
@@ -54,6 +54,7 @@ gk104_mc = {
        .intrs = gk104_mc_intrs,
        .intr_nonstall = true,
        .reset = gk104_mc_reset,
+       .device = &nv04_mc_device,
        .unk260 = gf100_mc_unk260,
 };
 
index 931985343ab52c35e6b6eb4a842dc197f2500c01..d98a6563a4117c9bd310cd5d0c75f8c814bdcdba 100644 (file)
@@ -29,6 +29,7 @@ gk20a_mc = {
        .intr = &gt215_mc_intr,
        .intrs = gk104_mc_intrs,
        .intr_nonstall = true,
+       .device = &nv04_mc_device,
        .reset = gk104_mc_reset,
 };
 
index 5dfdf75af255c63c75f6e293226735679bddc4d6..bffde40bb237d34627e3420ac13ad7c592dddefe 100644 (file)
@@ -90,6 +90,7 @@ gp100_mc = {
        .intr = &gp100_mc_intr,
        .intrs = gp100_mc_intrs,
        .intr_nonstall = true,
+       .device = &nv04_mc_device,
        .reset = gk104_mc_reset,
 };
 
index 6b83c6bf308c06b747ba915051c499596114670f..9bed9c5ea5d3919af92cbcb6994190c8d689ac12 100644 (file)
@@ -37,6 +37,7 @@ gp10b_mc = {
        .intr = &gp100_mc_intr,
        .intrs = gp100_mc_intrs,
        .intr_nonstall = true,
+       .device = &nv04_mc_device,
        .reset = gk104_mc_reset,
 };
 
index 330ef92f5e504aa6634fdde02d31e374f5268b65..41e17a4703885e72d03720dd173de71b52f43de0 100644 (file)
@@ -83,6 +83,7 @@ gt215_mc = {
        .init = nv50_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = gt215_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = gt215_mc_reset,
 };
 
index 00adf6833d265ce70d16b22333dcec60a714a989..04809caf36d6a141a1b4cf2ffbd472a782bf212c 100644 (file)
@@ -30,6 +30,34 @@ nv04_mc_reset[] = {
        {}
 };
 
+static void
+nv04_mc_device_disable(struct nvkm_mc *mc, u32 mask)
+{
+       nvkm_mask(mc->subdev.device, 0x000200, mask, 0x00000000);
+}
+
+static void
+nv04_mc_device_enable(struct nvkm_mc *mc, u32 mask)
+{
+       struct nvkm_device *device = mc->subdev.device;
+
+       nvkm_mask(device, 0x000200, mask, mask);
+       nvkm_rd32(device, 0x000200);
+}
+
+static bool
+nv04_mc_device_enabled(struct nvkm_mc *mc, u32 mask)
+{
+       return (nvkm_rd32(mc->subdev.device, 0x000200) & mask) == mask;
+}
+
+const struct nvkm_mc_device_func
+nv04_mc_device = {
+       .enabled = nv04_mc_device_enabled,
+       .enable = nv04_mc_device_enable,
+       .disable = nv04_mc_device_disable,
+};
+
 static const struct nvkm_intr_data
 nv04_mc_intrs[] = {
        { NVKM_ENGINE_DISP , 0, 0, 0x01010000, true },
@@ -98,6 +126,7 @@ nv04_mc = {
        .init = nv04_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = nv04_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = nv04_mc_reset,
 };
 
index 1cef78827f570b10dac7db4bb801ca8bed5292d5..6a3e2f4753ef07c3bf897eb410a2782b1d20cfe6 100644 (file)
@@ -38,6 +38,7 @@ nv11_mc = {
        .init = nv04_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = nv11_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = nv04_mc_reset,
 };
 
index ac70c359bce0a23d5fae60147914eaf1faa96ac3..2edc1cb0e379cfb548b93d94ac784d7228db5e69 100644 (file)
@@ -47,6 +47,7 @@ nv17_mc = {
        .init = nv04_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = nv17_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = nv17_mc_reset,
 };
 
index 0a054459a949ad444d58a723a29cf8303485922e..649a9fcc0a2fe97d7ba787f4b8db745b57740259 100644 (file)
@@ -42,6 +42,7 @@ nv44_mc = {
        .init = nv44_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = nv17_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = nv17_mc_reset,
 };
 
index 6a02ed754c3fbbb986bcf85ded6d2c3862ebd079..a42d20206e37eaff7e0c61f4c7e5d9c218cdf837 100644 (file)
@@ -49,6 +49,7 @@ nv50_mc = {
        .init = nv50_mc_init,
        .intr = &nv04_mc_intr,
        .intrs = nv50_mc_intrs,
+       .device = &nv04_mc_device,
        .reset = nv17_mc_reset,
 };
 
index 3ecfe9b4fb05fa4ecb3adc8166a68c54e77c0840..7f38d54b4bc2a56c02110450e2d4aa9e79900352 100644 (file)
@@ -21,7 +21,14 @@ struct nvkm_mc_func {
        const struct nvkm_intr_data *intrs;
        bool intr_nonstall;
 
+       const struct nvkm_mc_device_func {
+               bool (*enabled)(struct nvkm_mc *, u32 mask);
+               void (*enable)(struct nvkm_mc *, u32 mask);
+               void (*disable)(struct nvkm_mc *, u32 mask);
+       } *device;
+
        const struct nvkm_mc_map *reset;
+
        void (*unk260)(struct nvkm_mc *, u32);
 };
 
@@ -30,6 +37,7 @@ extern const struct nvkm_intr_func nv04_mc_intr;
 bool nv04_mc_intr_pending(struct nvkm_intr *);
 void nv04_mc_intr_unarm(struct nvkm_intr *);
 void nv04_mc_intr_rearm(struct nvkm_intr *);
+extern const struct nvkm_mc_device_func nv04_mc_device;
 extern const struct nvkm_mc_map nv04_mc_reset[];
 
 extern const struct nvkm_intr_data nv17_mc_intrs[];