#size-cells = <2>;
                ranges;
 
-               gpio0: gpio0@ff040000 {
+               gpio0: gpio@ff040000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff040000 0x0 0x100>;
                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio1: gpio1@ff250000 {
+               gpio1: gpio@ff250000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff250000 0x0 0x100>;
                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio2: gpio2@ff260000 {
+               gpio2: gpio@ff260000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff260000 0x0 0x100>;
                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio3: gpio3@ff270000 {
+               gpio3: gpio@ff270000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff270000 0x0 0x100>;
                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 
                #size-cells = <2>;
                ranges;
 
-               gpio0: gpio0@ff220000 {
+               gpio0: gpio@ff220000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff220000 0x0 0x100>;
                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio1: gpio1@ff230000 {
+               gpio1: gpio@ff230000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff230000 0x0 0x100>;
                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio2: gpio2@ff240000 {
+               gpio2: gpio@ff240000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff240000 0x0 0x100>;
                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio3: gpio3@ff250000 {
+               gpio3: gpio@ff250000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff250000 0x0 0x100>;
                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio4: gpio4@ff260000 {
+               gpio4: gpio@ff260000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff260000 0x0 0x100>;
                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 
                #size-cells = <2>;
                ranges;
 
-               gpio0: gpio0@ff210000 {
+               gpio0: gpio@ff210000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff210000 0x0 0x100>;
                        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio1: gpio1@ff220000 {
+               gpio1: gpio@ff220000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff220000 0x0 0x100>;
                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio2: gpio2@ff230000 {
+               gpio2: gpio@ff230000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff230000 0x0 0x100>;
                        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                };
 
-               gpio3: gpio3@ff240000 {
+               gpio3: gpio@ff240000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff240000 0x0 0x100>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 
                #size-cells = <0x2>;
                ranges;
 
-               gpio0: gpio0@ff750000 {
+               gpio0: gpio@ff750000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff750000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO0>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio1: gpio1@ff780000 {
+               gpio1: gpio@ff780000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff780000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO1>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio2: gpio2@ff790000 {
+               gpio2: gpio@ff790000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff790000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO2>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio3: gpio3@ff7a0000 {
+               gpio3: gpio@ff7a0000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff7a0000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO3>;
 
                #size-cells = <2>;
                ranges;
 
-               gpio0: gpio0@ff720000 {
+               gpio0: gpio@ff720000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff720000 0x0 0x100>;
                        clocks = <&pmucru PCLK_GPIO0_PMU>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio1: gpio1@ff730000 {
+               gpio1: gpio@ff730000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff730000 0x0 0x100>;
                        clocks = <&pmucru PCLK_GPIO1_PMU>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio2: gpio2@ff780000 {
+               gpio2: gpio@ff780000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff780000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO2>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio3: gpio3@ff788000 {
+               gpio3: gpio@ff788000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff788000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO3>;
                        #interrupt-cells = <0x2>;
                };
 
-               gpio4: gpio4@ff790000 {
+               gpio4: gpio@ff790000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x0 0xff790000 0x0 0x100>;
                        clocks = <&cru PCLK_GPIO4>;