drm/amd/display: add debug option for ExtendedVBlank DLG adjust
authorMuhammad Ahmed <ahmed.ahmed@amd.com>
Wed, 6 Dec 2023 23:07:57 +0000 (18:07 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 19 Dec 2023 19:59:02 +0000 (14:59 -0500)
[why & how]
Add new option for debug usage

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

index c87ec3e0a8cfdc278d76e5902f4d176bc2eed122..ce00a6eeb16400e4ddc188af15cb78b6dba1fada 100644 (file)
@@ -979,6 +979,7 @@ struct dc_debug_options {
        unsigned int ips2_eval_delay_us;
        unsigned int ips2_entry_delay_us;
        bool disable_timeout;
+       bool disable_extblankadj;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;
index 2c8eff815ec11458f20d925678315bdcfcc240a3..72c580ec650cfd13e76e41a70c476180ea4dfb7e 100644 (file)
@@ -2221,7 +2221,8 @@ void dcn20_optimize_bandwidth(
                        dc->clk_mgr,
                        context,
                        true);
-       if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
+       if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&
+               !dc->debug.disable_extblankadj) {
                for (i = 0; i < dc->res_pool->pipe_count; ++i) {
                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];