#ifndef __ASM_POINTER_AUTH_H
 #define __ASM_POINTER_AUTH_H
 
+#include <linux/bitops.h>
 #include <linux/random.h>
 
 #include <asm/cpufeature.h>
+#include <asm/memory.h>
 #include <asm/sysreg.h>
 
 #ifdef CONFIG_ARM64_PTR_AUTH
                __ptrauth_key_install(APGA, keys->apga);
 }
 
+/*
+ * The EL0 pointer bits used by a pointer authentication code.
+ * This is dependent on TBI0 being enabled, or bits 63:56 would also apply.
+ */
+#define ptrauth_user_pac_mask()        GENMASK(54, vabits_user)
+
 #define ptrauth_thread_init_user(tsk)                                  \
 do {                                                                   \
        struct task_struct *__ptiu_tsk = (tsk);                         \
 
 #include <asm/debug-monitors.h>
 #include <asm/fpsimd.h>
 #include <asm/pgtable.h>
+#include <asm/pointer_auth.h>
 #include <asm/stacktrace.h>
 #include <asm/syscall.h>
 #include <asm/traps.h>
 
 #endif /* CONFIG_ARM64_SVE */
 
+#ifdef CONFIG_ARM64_PTR_AUTH
+static int pac_mask_get(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       void *kbuf, void __user *ubuf)
+{
+       /*
+        * The PAC bits can differ across data and instruction pointers
+        * depending on TCR_EL1.TBID*, which we may make use of in future, so
+        * we expose separate masks.
+        */
+       unsigned long mask = ptrauth_user_pac_mask();
+       struct user_pac_mask uregs = {
+               .data_mask = mask,
+               .insn_mask = mask,
+       };
+
+       if (!system_supports_address_auth())
+               return -EINVAL;
+
+       return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &uregs, 0, -1);
+}
+#endif /* CONFIG_ARM64_PTR_AUTH */
+
 enum aarch64_regset {
        REGSET_GPR,
        REGSET_FPR,
 #ifdef CONFIG_ARM64_SVE
        REGSET_SVE,
 #endif
+#ifdef CONFIG_ARM64_PTR_AUTH
+       REGSET_PAC_MASK,
+#endif
 };
 
 static const struct user_regset aarch64_regsets[] = {
                .get_size = sve_get_size,
        },
 #endif
+#ifdef CONFIG_ARM64_PTR_AUTH
+       [REGSET_PAC_MASK] = {
+               .core_note_type = NT_ARM_PAC_MASK,
+               .n = sizeof(struct user_pac_mask) / sizeof(u64),
+               .size = sizeof(u64),
+               .align = sizeof(u64),
+               .get = pac_mask_get,
+               /* this cannot be set dynamically */
+       },
+#endif
 };
 
 static const struct user_regset_view user_aarch64_view = {
 
 #define NT_ARM_HW_WATCH        0x403           /* ARM hardware watchpoint registers */
 #define NT_ARM_SYSTEM_CALL     0x404   /* ARM system call number */
 #define NT_ARM_SVE     0x405           /* ARM Scalable Vector Extension registers */
+#define NT_ARM_PAC_MASK                0x406   /* ARM pointer authentication code masks */
 #define NT_ARC_V2      0x600           /* ARCv2 accumulator/extra registers */
 #define NT_VMCOREDD    0x700           /* Vmcore Device Dump Note */
 #define NT_MIPS_DSP    0x800           /* MIPS DSP ASE registers */