RDMA/hns: Fix incorrect clearing of interrupt status register
authorHaoyue Xu <xuhaoyue1@hisilicon.com>
Thu, 14 Jul 2022 13:43:51 +0000 (21:43 +0800)
committerLeon Romanovsky <leonro@nvidia.com>
Mon, 18 Jul 2022 11:16:27 +0000 (14:16 +0300)
The driver will clear all the interrupts in the same area
when the driver handles the interrupt of type AEQ overflow.
It should only set the interrupt status bit of type AEQ overflow.

Fixes: a5073d6054f7 ("RDMA/hns: Add eq support of hip08")
Link: https://lore.kernel.org/r/20220714134353.16700-4-liangwenpeng@huawei.com
Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
drivers/infiniband/hw/hns/hns_roce_hw_v2.c

index bb6073635c533e3e66144b6d40f17ce8822bf871..35bf58fcaeb3f8ed91c74fea2db8bcdbf252fa3b 100644 (file)
@@ -6001,8 +6001,8 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
 
                dev_err(dev, "AEQ overflow!\n");
 
-               int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S;
-               roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
+               roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
+                          1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
 
                /* Set reset level for reset_event() */
                if (ops->set_default_reset_request)