drm/amdgpu: Use the right method to get IP version
authorLijo Lazar <lijo.lazar@amd.com>
Fri, 1 Dec 2023 11:43:46 +0000 (17:13 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 13 Dec 2023 20:09:53 +0000 (15:09 -0500)
Replace direct usage of adev->ip_versions with amdgpu_ip_version.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

index f58fb719292d1e7fe41b5badd46800c433478106..85ed0d66a0298b46fb157b3e36e4db59f9b553a9 100644 (file)
@@ -1599,7 +1599,7 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
        if (adev->mman.keep_stolen_vga_memory)
                return false;
 
-       return adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0);
+       return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0);
 }
 
 /*
index 3a632c3b1a2cdc4a9d0fce475199c6b034795f42..0dcff2889e25d2b8883a39eaf9d09755bb1c2373 100644 (file)
@@ -1099,7 +1099,8 @@ bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev)
 {
        bool xnack_mode = true;
 
-       if (amdgpu_sriov_vf(adev) && adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
+       if (amdgpu_sriov_vf(adev) &&
+           amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
                xnack_mode = false;
 
        return xnack_mode;
index 2ac5820e9c9241431b1fda853dddc9242c04790e..473a774294cee76356717f7eb5e3ddaabbf76c11 100644 (file)
@@ -883,7 +883,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
         * GRBM interface.
         */
        if ((vmhub == AMDGPU_GFXHUB(0)) &&
-           (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
+           (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
                RREG32_NO_KIQ(req);
 
        for (j = 0; j < adev->usec_timeout; j++) {
index 80346bebb7fc0e1a0997178a061ff2617c13427b..e819d05755b3f47de247fac4abb3877641cbcf67 100644 (file)
@@ -1712,7 +1712,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
 
        /* Enable DWB for tested platforms only */
-       if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0))
+       if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
                init_data.num_virtual_links = 1;
 
        INIT_LIST_HEAD(&adev->dm.da_list);
@@ -8939,7 +8939,7 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm,
        }
 
        wb_info->mcif_buf_params.p_vmid = 1;
-       if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0)) {
+       if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) {
                wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
                wb_info->mcif_warmup_params.region_size =
                        wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
@@ -9891,7 +9891,8 @@ static bool should_reset_plane(struct drm_atomic_state *state,
         * TODO: Remove this hack for all asics once it proves that the
         * fast updates works fine on DCN3.2+.
         */
-       if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset)
+       if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) &&
+           state->allow_modeset)
                return true;
 
        /* Exit early if we know that we're adding or removing the plane. */
index d8f8ad0e71375145ac230e247ba20142b3e2de52..4894f7ee737b41dd0e81503b5cb7f3fc1182a6e6 100644 (file)
@@ -224,7 +224,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
        if (smu->is_apu)
                adev->pm.fw_version = smu_version;
 
-       switch (adev->ip_versions[MP1_HWIP][0]) {
+       switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
        case IP_VERSION(14, 0, 2):
                smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
                break;
@@ -235,7 +235,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
                break;
        default:
                dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
-                       adev->ip_versions[MP1_HWIP][0]);
+                       amdgpu_ip_version(adev, MP1_HWIP, 0));
                smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;
                break;
        }
@@ -733,7 +733,7 @@ int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
        int ret = 0;
        struct amdgpu_device *adev = smu->adev;
 
-       switch (adev->ip_versions[MP1_HWIP][0]) {
+       switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
        case IP_VERSION(14, 0, 2):
        case IP_VERSION(14, 0, 0):
                if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))