arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.BigEnd

For some reason we refer to ID_AA64MMFR0_EL1.BigEnd as BIGENDEL. Remove the
EL from the name, bringing the naming into sync with DDI0487H.a. Due to the
large amount of MixedCase in this register which isn't really consistent
with either the kernel style or the majority of the architecture the use of
upper case is preserved. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-9-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 214325a7f6276e871f651017e85c579ad4e6e10f..d7b96dc9364b128e4decfcf2b19f281481cad287 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -597,7 +597,7 @@ static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
 
 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
 {
-       return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL_SHIFT) == 0x1 ||
+       return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGEND_SHIFT) == 0x1 ||
                cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;
 }
 
@@ -738,7 +738,7 @@ static inline bool system_supports_mixed_endian(void)
 
        mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        val = cpuid_feature_extract_unsigned_field(mmfr0,
-                                               ID_AA64MMFR0_EL1_BIGENDEL_SHIFT);
+                                               ID_AA64MMFR0_EL1_BIGEND_SHIFT);
 
        return val == 0x1;
 }

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e72bab4452e98053e77b4e61645a3bcd29467c96..f1430c77911ab2901a80933548f589f44b0c9557 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -744,7 +744,7 @@
 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT         20
 #define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT       16
 #define ID_AA64MMFR0_EL1_SNSMEM_SHIFT          12
-#define ID_AA64MMFR0_EL1_BIGENDEL_SHIFT                8
+#define ID_AA64MMFR0_EL1_BIGEND_SHIFT          8
 #define ID_AA64MMFR0_EL1_ASID_SHIFT            4
 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT         0
 

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2e19cbdab50a68037537f22d8123817b6bac4990..def03583523b69776dbf28da2a4b46cb7558217e 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -351,7 +351,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
        /* Linux shouldn't care about secure memory */
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASID_SHIFT, 4, 0),
        /*
         * Differing PARange is fine as long as all peripherals and memory are mapped

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index fad5406fc71ab5d8e8d67a2858a396b6dab42344..0ece26707fc0f52ebf505020a565ebe7e81da8f0 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -74,7 +74,7 @@
  * - Non-context synchronizing exception entry and exit
  */
 #define PVM_ID_AA64MMFR0_ALLOW (\
-       ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \
        ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \
        ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \
        ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \