clk: renesas: r8a779g0: Add RPC-IF clock

Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF)
on the Renesas R-Car V4H (R8A779G0) SoC.

While at it, fix table alignment in the definition of the related
RPCSRC internal clock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f0609c82e742865be753b67a0a6080f193f405ad.1665583328.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 390162a07595a681dbeb30138d49b82b91940953..5cc0dc9149bcb7d526544b44616ce3e614c6120b 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -91,7 +91,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
        DEF_RATE(".oco",        CLK_OCO,        32768),
 
-       DEF_BASE(".rpcsrc",     CLK_RPCSRC,             CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC,     CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
        DEF_FIXED(".vio",       CLK_VIO,        CLK_PLL5_DIV2,  3, 1),
        DEF_FIXED(".vc",        CLK_VC,         CLK_PLL5_DIV2,  3, 1),
 
@@ -177,6 +177,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("msi4",         622,    R8A779G0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779G0_CLK_MSO),
        DEF_MOD("pwm",          628,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("rpc-if",       629,    R8A779G0_CLK_RPCD2),
        DEF_MOD("scif0",        702,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("scif1",        703,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("scif3",        704,    R8A779G0_CLK_SASYNCPERD4),