x86/mce: Drop AMD-specific "DEFERRED" case from Intel severity rule list
authorTony Luck <tony.luck@intel.com>
Wed, 30 Sep 2020 02:13:13 +0000 (19:13 -0700)
committerBorislav Petkov <bp@suse.de>
Wed, 30 Sep 2020 05:49:58 +0000 (07:49 +0200)
Way back in v3.19 Intel and AMD shared the same machine check severity
grading code. So it made sense to add a case for AMD DEFERRED errors in
commit

  e3480271f592 ("x86, mce, severity: Extend the the mce_severity mechanism to handle UCNA/DEFERRED error")

But later in v4.2 AMD switched to a separate grading function in
commit

  bf80bbd7dcf5 ("x86/mce: Add an AMD severities-grading function")

Belatedly drop the DEFERRED case from the Intel rule list.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200930021313.31810-3-tony.luck@intel.com
arch/x86/kernel/cpu/mce/severity.c

index 567ce09a02868d23c72989396d71acd067e0e677..e0722461bb579a1196b00db61205cbfcb10719a3 100644 (file)
@@ -96,10 +96,6 @@ static struct severity {
                PANIC, "In kernel and no restart IP",
                EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
                ),
-       MCESEV(
-               DEFERRED, "Deferred error",
-               NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
-               ),
        MCESEV(
                KEEP, "Corrected error",
                NOSER, BITCLR(MCI_STATUS_UC)