ARM: dts: rockchip: Add power-controller for RK3128

Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231204153547.97877-2-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index c0c9f0eaffa387a335d3843bd46763866f2c49fa..0676d8b22a1eb775088deb7768d5ac4da19d29c4 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
 
 / {
        compatible = "rockchip,rk3128";
@@ -133,6 +134,93 @@
        pmu: syscon@100a0000 {
                compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
                reg = <0x100a0000 0x1000>;
+
+               power: power-controller {
+                       compatible = "rockchip,rk3128-power-controller";
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       power-domain@RK3128_PD_VIO {
+                               reg = <RK3128_PD_VIO>;
+                               clocks = <&cru ACLK_CIF>,
+                                        <&cru HCLK_CIF>,
+                                        <&cru DCLK_EBC>,
+                                        <&cru HCLK_EBC>,
+                                        <&cru ACLK_IEP>,
+                                        <&cru HCLK_IEP>,
+                                        <&cru ACLK_LCDC0>,
+                                        <&cru HCLK_LCDC0>,
+                                        <&cru PCLK_MIPI>,
+                                        <&cru ACLK_RGA>,
+                                        <&cru HCLK_RGA>,
+                                        <&cru ACLK_VIO0>,
+                                        <&cru ACLK_VIO1>,
+                                        <&cru HCLK_VIO>,
+                                        <&cru HCLK_VIO_H2P>,
+                                        <&cru DCLK_VOP>,
+                                        <&cru SCLK_VOP>;
+                               pm_qos = <&qos_ebc>,
+                                        <&qos_iep>,
+                                        <&qos_lcdc>,
+                                        <&qos_rga>,
+                                        <&qos_vip>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3128_PD_VIDEO {
+                               reg = <RK3128_PD_VIDEO>;
+                               clocks = <&cru ACLK_VDPU>,
+                                        <&cru HCLK_VDPU>,
+                                        <&cru ACLK_VEPU>,
+                                        <&cru HCLK_VEPU>,
+                                        <&cru SCLK_HEVC_CORE>;
+                               pm_qos = <&qos_vpu>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3128_PD_GPU {
+                               reg = <RK3128_PD_GPU>;
+                               clocks = <&cru ACLK_GPU>;
+                               pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
+                       };
+               };
+       };
+
+       qos_gpu: qos@1012d000 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012d000 0x20>;
+       };
+
+       qos_vpu: qos@1012e000 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012e000 0x20>;
+       };
+
+       qos_rga: qos@1012f000 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012f000 0x20>;
+       };
+
+       qos_ebc: qos@1012f080 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012f080 0x20>;
+       };
+
+       qos_iep: qos@1012f100 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012f100 0x20>;
+       };
+
+       qos_lcdc: qos@1012f180 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012f180 0x20>;
+       };
+
+       qos_vip: qos@1012f200 {
+               compatible = "rockchip,rk3128-qos", "syscon";
+               reg = <0x1012f200 0x20>;
        };
 
        gic: interrupt-controller@10139000 {