ARM: dts: rtd1195: Introduce r-bus

Model Realtek's register bus in DT.

Signed-off-by: Andreas Färber <afaerber@suse.de>

diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
index 0d7c2be750f6fc2d4ad0ff9c6924f96972923430..a8f7b9caacbab8cbcbe9f4874a9c53e935ba8f7b 100644 (file)
--- a/arch/arm/boot/dts/rtd1195.dtsi
+++ b/arch/arm/boot/dts/rtd1195.dtsi
@@ -93,28 +93,36 @@
                         <0x18100000 0x18100000 0x01000000>,
                         <0x80000000 0x80000000 0x80000000>;
 
-               wdt: watchdog@18007680 {
-                       compatible = "realtek,rtd1295-watchdog";
-                       reg = <0x18007680 0x100>;
-                       clocks = <&osc27M>;
-               };
-
-               uart0: serial@18007800 {
-                       compatible = "snps,dw-apb-uart";
-                       reg = <0x18007800 0x400>;
-                       reg-shift = <2>;
-                       reg-io-width = <4>;
-                       clock-frequency = <27000000>;
-                       status = "disabled";
-               };
-
-               uart1: serial@1801b200 {
-                       compatible = "snps,dw-apb-uart";
-                       reg = <0x1801b200 0x100>;
-                       reg-shift = <2>;
-                       reg-io-width = <4>;
-                       clock-frequency = <27000000>;
-                       status = "disabled";
+               rbus: bus@18000000 {
+                       compatible = "simple-bus";
+                       reg = <0x18000000 0x70000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x18000000 0x70000>;
+
+                       wdt: watchdog@7680 {
+                               compatible = "realtek,rtd1295-watchdog";
+                               reg = <0x7680 0x100>;
+                               clocks = <&osc27M>;
+                       };
+
+                       uart0: serial@7800 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x7800 0x400>;
+                               reg-shift = <2>;
+                               reg-io-width = <4>;
+                               clock-frequency = <27000000>;
+                               status = "disabled";
+                       };
+
+                       uart1: serial@1b200 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x1b200 0x100>;
+                               reg-shift = <2>;
+                               reg-io-width = <4>;
+                               clock-frequency = <27000000>;
+                               status = "disabled";
+                       };
                };
 
                gic: interrupt-controller@ff011000 {