unsigned long   flags;
 };
 
-#define CLK_FIXED_RATE_PARENT_ACCURACY         BIT(0)
+#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
 
 extern const struct clk_ops clk_fixed_rate_ops;
 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
 
 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
 
-#define CLK_FRAC_DIVIDER_ZERO_BASED            BIT(0)
-#define CLK_FRAC_DIVIDER_BIG_ENDIAN            BIT(1)
+#define CLK_FRAC_DIVIDER_ZERO_BASED    BIT(0)
+#define CLK_FRAC_DIVIDER_BIG_ENDIAN    BIT(1)
 
 extern const struct clk_ops clk_fractional_divider_ops;
 struct clk *clk_register_fractional_divider(struct device *dev,
 
 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
 
-#define CLK_MULTIPLIER_ZERO_BYPASS             BIT(0)
+#define CLK_MULTIPLIER_ZERO_BYPASS     BIT(0)
 #define CLK_MULTIPLIER_ROUND_CLOSEST   BIT(1)
-#define CLK_MULTIPLIER_BIG_ENDIAN              BIT(2)
+#define CLK_MULTIPLIER_BIG_ENDIAN      BIT(2)
 
 extern const struct clk_ops clk_multiplier_ops;