perf/x86/intel: Increase max number of the fixed counters

The new PEBS format 5 implies that the number of the fixed counters can
be up to 16. The current INTEL_PMC_MAX_FIXED is still 4. If the current
kernel runs on a future platform which has more than 4 fixed counters,
a warning will be triggered. The number of the fixed counters will be
clipped to 4. Users have to upgrade the kernel to access the new fixed
counters.

Add a new default constraint for PerfMon v5 and up, which can support
up to 16 fixed counters. The pseudo-encoding is applied for the fixed
counters 4 and later. The user can have generic support for the new
fixed counters on the future platfroms without updating the kernel.

Increase the INTEL_PMC_MAX_FIXED to 16.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1643750603-100733-3-git-send-email-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c91434056c29895c1cb289870c824c5a95769632..88dcfb46c797f303c8221946a2d8845dfdcc44f4 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -181,6 +181,27 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
        EVENT_CONSTRAINT_END
 };
 
+static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
+{
+       FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
+       FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
+       FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+       FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
+       FIXED_EVENT_CONSTRAINT(0x0500, 4),
+       FIXED_EVENT_CONSTRAINT(0x0600, 5),
+       FIXED_EVENT_CONSTRAINT(0x0700, 6),
+       FIXED_EVENT_CONSTRAINT(0x0800, 7),
+       FIXED_EVENT_CONSTRAINT(0x0900, 8),
+       FIXED_EVENT_CONSTRAINT(0x0a00, 9),
+       FIXED_EVENT_CONSTRAINT(0x0b00, 10),
+       FIXED_EVENT_CONSTRAINT(0x0c00, 11),
+       FIXED_EVENT_CONSTRAINT(0x0d00, 12),
+       FIXED_EVENT_CONSTRAINT(0x0e00, 13),
+       FIXED_EVENT_CONSTRAINT(0x0f00, 14),
+       FIXED_EVENT_CONSTRAINT(0x1000, 15),
+       EVENT_CONSTRAINT_END
+};
+
 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 {
        FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
@@ -6295,7 +6316,9 @@ __init int intel_pmu_init(void)
                        pr_cont("generic architected perfmon v1, ");
                        name = "generic_arch_v1";
                        break;
-               default:
+               case 2:
+               case 3:
+               case 4:
                        /*
                         * default constraints for v2 and up
                         */
@@ -6303,6 +6326,21 @@ __init int intel_pmu_init(void)
                        pr_cont("generic architected perfmon, ");
                        name = "generic_arch_v2+";
                        break;
+               default:
+                       /*
+                        * The default constraints for v5 and up can support up to
+                        * 16 fixed counters. For the fixed counters 4 and later,
+                        * the pseudo-encoding is applied.
+                        * The constraints may be cut according to the CPUID enumeration
+                        * by inserting the EVENT_CONSTRAINT_END.
+                        */
+                       if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED)
+                               x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
+                       intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1;
+                       x86_pmu.event_constraints = intel_v5_gen_event_constraints;
+                       pr_cont("generic architected perfmon, ");
+                       name = "generic_arch_v5+";
+                       break;
                }
        }
 

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8fc1b5003713fd67ba463dad79e324f47679bb05..58d9e4b1fa0add445ef39ff4032fc4ae5bde6a5c 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -7,7 +7,7 @@
  */
 
 #define INTEL_PMC_MAX_GENERIC                                 32
-#define INTEL_PMC_MAX_FIXED                                    4
+#define INTEL_PMC_MAX_FIXED                                   16
 #define INTEL_PMC_IDX_FIXED                                   32
 
 #define X86_PMC_IDX_MAX                                               64