if (cpu_has_ds) {
                unsigned int l1, l2;
                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+               if (!(l1 & (1<<11)))
+                       set_bit(X86_FEATURE_BTS, c->x86_capability);
                if (!(l1 & (1<<12)))
                        set_bit(X86_FEATURE_PEBS, c->x86_capability);
        }
 
 #define X86_FEATURE_UP         (3*32+8) /* SMP kernel running on UP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */
 #define X86_FEATURE_PEBS       (3*32+10) /* Precise-Event Based Sampling */
+#define X86_FEATURE_BTS                (3*32+11) /* Branch Trace Store */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */
 #define cpu_has_clflush               boot_cpu_has(X86_FEATURE_CLFLSH)
 #define cpu_has_ds            boot_cpu_has(X86_FEATURE_DS)
 #define cpu_has_pebs          boot_cpu_has(X86_FEATURE_PEBS)
+#define cpu_has_bts           boot_cpu_has(X86_FEATURE_BTS)
 
 #endif /* __ASM_X8664_CPUFEATURE_H */