platform/x86/intel: pmc/core: Add Latency Tolerance Reporting (LTR) support to Alder...

Add support to show the Latency Tolerance Reporting for the IPs on
the Alder Lake PCH as reported by the PMC. This LTR support on
Alder Lake is slightly different from the Cannon lake PCH that is being
reused by all platforms till Tiger Lake.

Cc: Chao Qin <chao.qin@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Link: https://lore.kernel.org/r/5ca3ea090b53a9bf918b055447ab5c8ef2925cc4.1629091915.git.gayatri.kammela@intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 81b8049c7023b2ed455f4a8ac2ff3cbbd71ecbbd..a5e8c5cca98da117fd4958dde82ec4fa4c019fa5 100644 (file)
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -699,10 +699,48 @@ static const struct pmc_bit_map *ext_adl_pfear_map[] = {
        NULL
 };
 
+static const struct pmc_bit_map adl_ltr_show_map[] = {
+       {"SOUTHPORT_A",         CNP_PMC_LTR_SPA},
+       {"SOUTHPORT_B",         CNP_PMC_LTR_SPB},
+       {"SATA",                CNP_PMC_LTR_SATA},
+       {"GIGABIT_ETHERNET",    CNP_PMC_LTR_GBE},
+       {"XHCI",                CNP_PMC_LTR_XHCI},
+       {"SOUTHPORT_F",         ADL_PMC_LTR_SPF},
+       {"ME",                  CNP_PMC_LTR_ME},
+       /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+       {"SATA1",               CNP_PMC_LTR_EVA},
+       {"SOUTHPORT_C",         CNP_PMC_LTR_SPC},
+       {"HD_AUDIO",            CNP_PMC_LTR_AZ},
+       {"CNV",                 CNP_PMC_LTR_CNV},
+       {"LPSS",                CNP_PMC_LTR_LPSS},
+       {"SOUTHPORT_D",         CNP_PMC_LTR_SPD},
+       {"SOUTHPORT_E",         CNP_PMC_LTR_SPE},
+       {"SATA2",               CNP_PMC_LTR_CAM},
+       {"ESPI",                CNP_PMC_LTR_ESPI},
+       {"SCC",                 CNP_PMC_LTR_SCC},
+       {"ISH",                 CNP_PMC_LTR_ISH},
+       {"UFSX2",               CNP_PMC_LTR_UFSX2},
+       {"EMMC",                CNP_PMC_LTR_EMMC},
+       /*
+        * Check intel_pmc_core_ids[] users of cnp_reg_map for
+        * a list of core SoCs using this.
+        */
+       {"WIGIG",               ICL_PMC_LTR_WIGIG},
+       {"THC0",                TGL_PMC_LTR_THC0},
+       {"THC1",                TGL_PMC_LTR_THC1},
+       {"SOUTHPORT_G",         CNP_PMC_LTR_RESERVED},
+
+       /* Below two cannot be used for LTR_IGNORE */
+       {"CURRENT_PLATFORM",    CNP_PMC_LTR_CUR_PLT},
+       {"AGGREGATED_SYSTEM",   CNP_PMC_LTR_CUR_ASLT},
+       {}
+};
+
 static const struct pmc_reg_map adl_reg_map = {
        .pfear_sts = ext_adl_pfear_map,
        .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
        .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+       .ltr_show_sts = adl_ltr_show_map,
        .msr_sts = msr_map,
        .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
        .regmap_length = CNP_PMC_MMIO_REG_LEN,
@@ -710,6 +748,7 @@ static const struct pmc_reg_map adl_reg_map = {
        .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
        .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
        .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+       .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
 };
 
 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)

diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 8972363b57b440d80f0f227000e8e30f5d49ba96..6863f4de3070661919069480e26834ae3e3cbf85 100644 (file)
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -199,6 +199,8 @@ enum ppfear_regs {
 #define TGL_NUM_IP_IGN_ALLOWED                 23
 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2                61      /* 30.5us * 2 */
 
+#define ADL_PMC_LTR_SPF                                0x1C00
+#define ADL_NUM_IP_IGN_ALLOWED                 23
 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET      0x1098
 
 /*