examples:
- |
spi@c1108d80 {
- compatible = "amlogic,meson-gx-spicc";
- reg = <0xc1108d80 0x80>;
- interrupts = <112>;
- clocks = <&clk81>;
- clock-names = "core";
- #address-cells = <1>;
- #size-cells = <0>;
-
- display@0 {
- compatible = "lg,lg4573";
- spi-max-frequency = <1000000>;
- reg = <0>;
- };
+ compatible = "amlogic,meson-gx-spicc";
+ reg = <0xc1108d80 0x80>;
+ interrupts = <112>;
+ clocks = <&clk81>;
+ clock-names = "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "lg,lg4573";
+ spi-max-frequency = <1000000>;
+ reg = <0>;
+ };
};
examples:
- |
spi@c1108c80 {
- compatible = "amlogic,meson6-spifc";
- reg = <0xc1108c80 0x80>;
- clocks = <&clk81>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- flash: flash@0 {
- compatible = "spansion,m25p80", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- };
+ compatible = "amlogic,meson6-spifc";
+ reg = <0xc1108c80 0x80>;
+ clocks = <&clk81>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash: flash@0 {
+ compatible = "spansion,m25p80", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
};
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
flash@0 {
- reg = < 0 >;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <2>;
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
};
flash@1 {
- reg = < 1 >;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <2>;
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
};
flash@2 {
- reg = < 2 >;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <2>;
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
};
};
examples:
- | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
spi@f03e3400 {
- compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
- reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
- reg-names = "mspi", "bspi", "cs_reg";
- interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
- interrupt-parent = <&gic>;
- interrupt-names = "mspi_done",
- "mspi_halted",
- "spi_lr_fullness_reached",
- "spi_lr_session_aborted",
- "spi_lr_impatient",
- "spi_lr_session_done",
- "spi_lr_overread";
- clocks = <&hif_spi>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
-
- flash@0 {
- #size-cells = <0x2>;
- #address-cells = <0x2>;
- compatible = "m25p80";
- reg = <0x0>;
- spi-max-frequency = <0x2625a00>;
- spi-cpol;
- spi-cpha;
- };
+ compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
+ reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
+ reg-names = "mspi", "bspi", "cs_reg";
+ interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
+ interrupt-parent = <&gic>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread";
+ clocks = <&hif_spi>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ flash@0 {
+ #size-cells = <0x2>;
+ #address-cells = <0x2>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <0x2625a00>;
+ spi-cpol;
+ spi-cpha;
+ };
};
- | # BRCMSTB SoC: MSPI master for any SPI device
spi@f0416000 {
- clocks = <&upg_fixed>;
- compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
- reg = <0xf0416000 0x180>;
- reg-names = "mspi";
- interrupts = <0x14>;
- interrupt-parent = <&irq0_aon_intc>;
- interrupt-names = "mspi_done";
- #address-cells = <1>;
- #size-cells = <0>;
+ clocks = <&upg_fixed>;
+ compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
+ reg = <0xf0416000 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&irq0_aon_intc>;
+ interrupt-names = "mspi_done";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- | # iProc SoC
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@18027200 {
- compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
- reg = <0x18027200 0x184>,
- <0x18027000 0x124>,
- <0x1811c408 0x004>,
- <0x180273a0 0x01c>;
- reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mspi_done",
- "mspi_halted",
- "spi_lr_fullness_reached",
- "spi_lr_session_aborted",
- "spi_lr_impatient",
- "spi_lr_session_done";
- clocks = <&iprocmed>;
- num-cs = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
+ reg = <0x18027200 0x184>,
+ <0x18027000 0x124>,
+ <0x1811c408 0x004>,
+ <0x180273a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done";
+ clocks = <&iprocmed>;
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- | # NS2 SoC
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@66470200 {
- compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
- reg = <0x66470200 0x184>,
- <0x66470000 0x124>,
- <0x67017408 0x004>,
- <0x664703a0 0x01c>;
- reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
- interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "spi_l1_intr";
- clocks = <&iprocmed>;
- num-cs = <2>;
+ compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
+ reg = <0x66470200 0x184>,
+ <0x66470000 0x124>,
+ <0x67017408 0x004>,
+ <0x664703a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+ interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "spi_l1_intr";
+ clocks = <&iprocmed>;
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
#address-cells = <1>;
- #size-cells = <0>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p80";
- reg = <0x0>;
- spi-max-frequency = <12500000>;
- spi-cpol;
- spi-cpha;
- };
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ spi-cpol;
+ spi-cpha;
+ };
};
examples:
- |
qspi: spi@ff705000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xff705000 0x1000>,
- <0xffa00000 0x1000>;
- interrupts = <0 151 4>;
- clocks = <&qspi_clk>;
- cdns,fifo-depth = <128>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x00000000>;
- resets = <&rst 0x1>, <&rst 0x2>;
- reset-names = "qspi", "qspi-ocp";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- };
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ resets = <&rst 0x1>, <&rst 0x2>;
+ reset-names = "qspi", "qspi-ocp";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ };
};
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@70410000 {
- compatible = "nvidia,tegra210-qspi";
- reg = <0x70410000 0x1000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA210_CLK_QSPI>,
- <&tegra_car TEGRA210_CLK_QSPI_PM>;
- clock-names = "qspi", "qspi_out";
- resets = <&tegra_car 211>;
- dmas = <&apbdma 5>, <&apbdma 5>;
- dma-names = "rx", "tx";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- spi-tx-bus-width = <2>;
- spi-rx-bus-width = <2>;
- nvidia,tx-clk-tap-delay = <0>;
- nvidia,rx-clk-tap-delay = <0>;
- };
+ compatible = "nvidia,tegra210-qspi";
+ reg = <0x70410000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_QSPI>,
+ <&tegra_car TEGRA210_CLK_QSPI_PM>;
+ clock-names = "qspi", "qspi_out";
+ resets = <&tegra_car 211>;
+ dmas = <&apbdma 5>, <&apbdma 5>;
+ dma-names = "rx", "tx";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ nvidia,tx-clk-tap-delay = <0>;
+ nvidia,rx-clk-tap-delay = <0>;
+ };
};
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
-
};
};
...
#include <dt-bindings/power/r8a7791-sysc.h>
qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7791", "renesas,qspi";
- reg = <0xe6b10000 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
+ compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+ reg = <0xe6b10000 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
- spi@9C002D80 {
+ spi@9c002d80 {
compatible = "sunplus,sp7021-spi";
- reg = <0x9C002D80 0x80>, <0x9C002E00 0x80>;
+ reg = <0x9c002d80 0x80>, <0x9c002e00 0x80>;
reg-names = "master", "slave";
interrupt-parent = <&intc>;
interrupt-names = "dma_w",
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
spi@4000b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI2_K>;
- resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 0 39 0x400 0x05>,
- <&dmamux1 1 40 0x400 0x05>;
- dma-names = "rx", "tx";
- cs-gpios = <&gpioa 11 0>;
-
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI2_K>;
+ resets = <&rcc SPI2_R>;
+ dmas = <&dmamux1 0 39 0x400 0x05>,
+ <&dmamux1 1 40 0x400 0x05>;
+ dma-names = "rx", "tx";
+ cs-gpios = <&gpioa 11 0>;
};
...
projects / linux.git / commitdiff