arm64/sysreg: Convert TRBLIMITR_EL1 register to automatic generation

This converts TRBLIMITR_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-9-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d699747a0363ee27d70a2f8e8cf7ebbc624c38f1..f97d08d8d8dae58659b37c1dd95de12d0045d769 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -227,10 +227,6 @@
 
 /*** End of Statistical Profiling Extension ***/
 
-/*
- * TRBE Registers
- */
-#define SYS_TRBLIMITR_EL1              sys_reg(3, 0, 9, 11, 0)
 #define SYS_TRBPTR_EL1                 sys_reg(3, 0, 9, 11, 1)
 #define SYS_TRBBASER_EL1               sys_reg(3, 0, 9, 11, 2)
 #define SYS_TRBSR_EL1                  sys_reg(3, 0, 9, 11, 3)
@@ -238,14 +234,6 @@
 #define SYS_TRBTRG_EL1                 sys_reg(3, 0, 9, 11, 6)
 #define SYS_TRBIDR_EL1                 sys_reg(3, 0, 9, 11, 7)
 
-#define TRBLIMITR_EL1_LIMIT_MASK       GENMASK_ULL(63, 12)
-#define TRBLIMITR_EL1_LIMIT_SHIFT      12
-#define TRBLIMITR_EL1_nVM              BIT(5)
-#define TRBLIMITR_EL1_TM_MASK          GENMASK(4, 3)
-#define TRBLIMITR_EL1_TM_SHIFT         3
-#define TRBLIMITR_EL1_FM_MASK          GENMASK(2, 1)
-#define TRBLIMITR_EL1_FM_SHIFT         1
-#define TRBLIMITR_EL1_E                        BIT(0)
 #define TRBPTR_EL1_PTR_MASK            GENMASK_ULL(63, 0)
 #define TRBPTR_EL1_PTR_SHIFT           0
 #define TRBBASER_EL1_BASE_MASK         GENMASK_ULL(63, 12)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 41462785020b9828164eeaac8a6851277f2aa0c6..fe2490713754f848461f0c27f4d5220066cb5ceb 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2255,3 +2255,21 @@ Sysreg   ICC_NMIAR1_EL1  3       0       12      9       5
 Res0   63:24
 Field  23:0    INTID
 EndSysreg
+
+Sysreg TRBLIMITR_EL1   3       0       9       11      0
+Field  63:12   LIMIT
+Res0   11:7
+Field  6       XE
+Field  5       nVM
+Enum   4:3     TM
+       0b00    STOP
+       0b01    IRQ
+       0b11    IGNR
+EndEnum
+Enum   2:1     FM
+       0b00    FILL
+       0b01    WRAP
+       0b11    CBUF
+EndEnum
+Field  0       E
+EndSysreg

diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
index d661b062293f188f78a455c4cc791977622bf8e7..77cbb5c6387833a3892112fc9a6aa3b778a62713 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-trbe.h
+++ b/drivers/hwtracing/coresight/coresight-trbe.h
@@ -84,15 +84,6 @@ static inline bool is_trbe_running(u64 trbsr)
        return !(trbsr & TRBSR_EL1_S);
 }
 
-#define TRBE_TRIG_MODE_STOP            0
-#define TRBE_TRIG_MODE_IRQ             1
-#define TRBLIMITR_EL1_TM_IGNR          3
-
-#define TRBLIMITR_EL1_FM_FILL          0
-#define TRBE_FILL_MODE_FILL            0
-#define TRBE_FILL_MODE_WRAP            1
-#define TRBE_FILL_MODE_CIRCULAR_BUFFER 3
-
 static inline bool get_trbe_flag_update(u64 trbidr)
 {
        return trbidr & TRBIDR_EL1_F;