arm64: dts: qcom: sm8550: Add GPU nodes

Add the required nodes to support the A740 GPU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20231127-topic-a7xx_dt-v2-3-2a437588e563@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index eaad6c5831c7626eb43c289413ecb96213e3cc0f..68627db507cfe8fc75ffb1cba7d0f2648a339897 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1985,6 +1985,128 @@
                        #reset-cells = <1>;
                };
 
+               gpu: gpu@3d00000 {
+                       compatible = "qcom,adreno-43050a01", "qcom,adreno";
+                       reg = <0x0 0x03d00000 0x0 0x40000>,
+                             <0x0 0x03d9e000 0x0 0x1000>,
+                             <0x0 0x03d61000 0x0 0x800>;
+                       reg-names = "kgsl_3d0_reg_memory",
+                                   "cx_mem",
+                                   "cx_dbgc";
+
+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       iommus = <&adreno_smmu 0 0x0>,
+                                <&adreno_smmu 1 0x0>;
+
+                       operating-points-v2 = <&gpu_opp_table>;
+
+                       qcom,gmu = <&gmu>;
+
+                       status = "disabled";
+
+                       zap-shader {
+                               memory-region = <&gpu_micro_code_mem>;
+                       };
+
+                       /* Speedbin needs more work on A740+, keep only lower freqs */
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-680000000 {
+                                       opp-hz = /bits/ 64 <680000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                               };
+
+                               opp-615000000 {
+                                       opp-hz = /bits/ 64 <615000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+                               };
+
+                               opp-550000000 {
+                                       opp-hz = /bits/ 64 <550000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                               };
+
+                               opp-475000000 {
+                                       opp-hz = /bits/ 64 <475000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+                               };
+
+                               opp-401000000 {
+                                       opp-hz = /bits/ 64 <401000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                               };
+
+                               opp-348000000 {
+                                       opp-hz = /bits/ 64 <348000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+                               };
+
+                               opp-295000000 {
+                                       opp-hz = /bits/ 64 <295000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+                               };
+
+                               opp-220000000 {
+                                       opp-hz = /bits/ 64 <220000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+                               };
+                       };
+               };
+
+               gmu: gmu@3d6a000 {
+                       compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
+                       reg = <0x0 0x03d6a000 0x0 0x35000>,
+                             <0x0 0x03d50000 0x0 0x10000>,
+                             <0x0 0x0b280000 0x0 0x10000>;
+                       reg-names = "gmu", "rscc", "gmu_pdc";
+
+                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hfi", "gmu";
+
+                       clocks = <&gpucc GPU_CC_AHB_CLK>,
+                                <&gpucc GPU_CC_CX_GMU_CLK>,
+                                <&gpucc GPU_CC_CXO_CLK>,
+                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                                <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+                                <&gpucc GPU_CC_DEMET_CLK>;
+                       clock-names = "ahb",
+                                     "gmu",
+                                     "cxo",
+                                     "axi",
+                                     "memnoc",
+                                     "hub",
+                                     "demet";
+
+                       power-domains = <&gpucc GPU_CC_CX_GDSC>,
+                                       <&gpucc GPU_CC_GX_GDSC>;
+                       power-domain-names = "cx",
+                                            "gx";
+
+                       iommus = <&adreno_smmu 5 0x0>;
+
+                       qcom,qmp = <&aoss_qmp>;
+
+                       operating-points-v2 = <&gmu_opp_table>;
+
+                       gmu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-500000000 {
+                                       opp-hz = /bits/ 64 <500000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                               };
+
+                               opp-200000000 {
+                                       opp-hz = /bits/ 64 <200000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                               };
+                       };
+               };
+
                gpucc: clock-controller@3d90000 {
                        compatible = "qcom,sm8550-gpucc";
                        reg = <0 0x03d90000 0 0xa000>;
@@ -1996,6 +2118,50 @@
                        #power-domain-cells = <1>;
                };
 
+               adreno_smmu: iommu@3da0000 {
+                       compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
+                                    "qcom,smmu-500", "arm,mmu-500";
+                       reg = <0x0 0x03da0000 0x0 0x40000>;
+                       #iommu-cells = <2>;
+                       #global-interrupts = <1>;
+                       interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+                                <&gpucc GPU_CC_AHB_CLK>;
+                       clock-names = "hlos",
+                                     "bus",
+                                     "iface",
+                                     "ahb";
+                       power-domains = <&gpucc GPU_CC_CX_GDSC>;
+                       dma-coherent;
+               };
+
                ipa: ipa@3f40000 {
                        compatible = "qcom,sm8550-ipa";