Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907' into...

target-arm:
 * cleanups converting to DEFINE_PROP_LINK
 * allwinner-a10: mark as not user-creatable
 * initial patches working towards ARMv8M support
 * implement generating aborts on memory transaction failures
 * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later

# gpg: Signature made Thu 07 Sep 2017 14:26:07 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits)
  target/arm: Add Jazelle feature
  target/arm: Implement new do_transaction_failed hook
  hw/arm: Set ignore_memory_transaction_failures for most ARM boards
  boards.h: Define new flag ignore_memory_transaction_failures
  target/arm: Implement BXNS, and banked stack pointers
  target/arm: Move regime_is_secure() to target/arm/internals.h
  target/arm: Make CFSR register banked for v8M
  target/arm: Make MMFAR banked for v8M
  target/arm: Make CCR register banked for v8M
  target/arm: Make MPU_CTRL register banked for v8M
  target/arm: Make MPU_RNR register banked for v8M
  target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
  target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
  target/arm: Make VTOR register banked for v8M
  nvic: Add NS alias SCS region
  target/arm: Make CONTROL register banked for v8M
  target/arm: Make FAULTMASK register banked for v8M
  target/arm: Make PRIMASK register banked for v8M
  target/arm: Make BASEPRI register banked for v8M
  target/arm: Add MMU indexes for secure v8M
  ...

# Conflicts:
#	target/arm/translate.c

diff --cc target/arm/translate.c
index 6946e56a3a47e44511e50276dcc1950cdae1c2a1,57899fa55b04263ae9280e71ca277ce8fdf436a3..ab1a12a1b8cf2e8033bdd797d30a847991382049
--- 1/target/arm/translate.c
--- 2/target/arm/translate.c
+++ b/target/arm/translate.c
@@@ -994,6 -994,25 +994,25 @@@ static inline void gen_bx_excret_final_
      gen_exception_internal(EXCP_EXCEPTION_EXIT);
  }
  
 -    s->is_jmp = DISAS_EXIT;
+ static inline void gen_bxns(DisasContext *s, int rm)
+ {
+     TCGv_i32 var = load_reg(s, rm);
+ 
+     /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
+      * we need to sync state before calling it, but:
+      *  - we don't need to do gen_set_pc_im() because the bxns helper will
+      *    always set the PC itself
+      *  - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
+      *    unless it's outside an IT block or the last insn in an IT block,
+      *    so we know that condexec == 0 (already set at the top of the TB)
+      *    is correct in the non-UNPREDICTABLE cases, and we can choose
+      *    "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
+      */
+     gen_helper_v7m_bxns(cpu_env, var);
+     tcg_temp_free_i32(var);
++    s->base.is_jmp = DISAS_EXIT;
+ }
+ 
  /* Variant of store_reg which uses branch&exchange logic when storing
     to r15 in ARM architecture v7 and above. The source must be a temporary
     and will be marked as dead. */
@@@ -11850,13 -11909,15 +11888,15 @@@ static int arm_tr_init_disas_context(Di
  #if !defined(CONFIG_USER_ONLY)
      dc->user = (dc->current_el == 0);
  #endif
 -    dc->ns = ARM_TBFLAG_NS(tb->flags);
 -    dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags);
 -    dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
 -    dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
 -    dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
 -    dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
 -    dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
 +    dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags);
 +    dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
 +    dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags);
 +    dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags);
 +    dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags);
 +    dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags);
 +    dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags);
+     dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+         regime_is_secure(env, dc->mmu_idx);
      dc->cp_regs = cpu->cp_regs;
      dc->features = env->features;
  

diff --cc target/arm/translate.h
Simple merge