status = "disabled";
        };
 
+       i2s1_8ch: i2s@fe410000 {
+               compatible = "rockchip,rk3568-i2s-tdm";
+               reg = <0x0 0xfe410000 0x0 0x1000>;
+               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+               assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
+               assigned-clock-rates = <1188000000>, <1188000000>;
+               clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
+                        <&cru HCLK_I2S1_8CH>;
+               clock-names = "mclk_tx", "mclk_rx", "hclk";
+               dmas = <&dmac1 3>, <&dmac1 2>;
+               dma-names = "rx", "tx";
+               resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
+               reset-names = "tx-m", "rx-m";
+               rockchip,grf = <&grf>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
+                            &i2s1m0_lrcktx &i2s1m0_lrckrx
+                            &i2s1m0_sdi0   &i2s1m0_sdi1
+                            &i2s1m0_sdi2   &i2s1m0_sdi3
+                            &i2s1m0_sdo0   &i2s1m0_sdo1
+                            &i2s1m0_sdo2   &i2s1m0_sdo3>;
+               #sound-dai-cells = <0>;
+               status = "disabled";
+       };
+
        dmac0: dmac@fe530000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x0 0xfe530000 0x0 0x4000>;