drm/i915/dg2: s/engine->i915/i915/ for engine workarounds

rcs_engine_wa_init() has a local 'i915' variable; we should use that
rather than 'engine->i915' for consistency with how we handle other
platforms.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128170125.4121819-1-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 379311aad020e8dccc73c95296072919981fa1d0..e18ed63b7b5fe63d2192a5952015529369d9bceb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2044,12 +2044,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
        struct drm_i915_private *i915 = engine->i915;
 
-       if (IS_DG2(engine->i915)) {
+       if (IS_DG2(i915)) {
                /* Wa_14015227452:dg2 */
                wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
                /* Wa_14013392000:dg2_g11 */
                wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
 
@@ -2057,15 +2057,15 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
-           IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
+           IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
                /* Wa_14012419201:dg2 */
                wa_masked_en(wal, GEN9_ROW_CHICKEN4,
                             GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) ||
-           IS_DG2_G11(engine->i915)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
+           IS_DG2_G11(i915)) {
                /*
                 * Wa_22012826095:dg2
                 * Wa_22013059131:dg2
@@ -2080,14 +2080,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        }
 
        /* Wa_1308578152:dg2_g10 when first gslice is fused off */
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) &&
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
            needs_wa_1308578152(engine)) {
                wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON,
                              GEN12_REPLAY_MODE_GRANULARITY);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
-           IS_DG2_G11(engine->i915)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+           IS_DG2_G11(i915)) {
                /* Wa_22013037850:dg2 */
                wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
                            DISABLE_128B_EVICTION_COMMAND_UDW);
@@ -2104,7 +2104,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                              LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
                /*
                 * Wa_1608949956:dg2_g10
                 * Wa_14010198302:dg2_g10
@@ -2123,7 +2123,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                       0, false);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
                /* Wa_22010430635:dg2 */
                wa_masked_en(wal,
                             GEN9_ROW_CHICKEN4,
@@ -2133,8 +2133,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
        }
 
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
-           IS_DG2_G11(engine->i915)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||
+           IS_DG2_G11(i915)) {
                /* Wa_22012654132:dg2 */
                wa_add(wal, GEN10_CACHE_MODE_SS, 0,
                       _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
@@ -2143,8 +2143,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        }
 
        /* Wa_14013202645:dg2 */
-       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) ||
-           IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
+           IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
                wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY);
 
        if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||