drm/msm/dpu: inline SSPP_BLK macros

To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/545377/
Link: https://lore.kernel.org/r/20230704022136.130522-11-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 6660a55909e7c47c7c8c4500246a4ad75e1ab70d..fd0081469a82ace11c4a766ab7a529bbaf49597d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg msm8998_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
-               msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
-               msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
-               msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
-               msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1ac,
+               .features = VIG_MSM8998_MASK,
+               .sblk = &msm8998_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x1ac,
+               .features = VIG_MSM8998_MASK,
+               .sblk = &msm8998_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x1ac,
+               .features = VIG_MSM8998_MASK,
+               .sblk = &msm8998_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x1ac,
+               .features = VIG_MSM8998_MASK,
+               .sblk = &msm8998_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1ac,
+               .features = DMA_MSM8998_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1ac,
+               .features = DMA_MSM8998_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1ac,
+               .features = DMA_CURSOR_MSM8998_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x1ac,
+               .features = DMA_CURSOR_MSM8998_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg msm8998_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 7da35be0a79cce6edbaf9a759112601d7f1c550b..9fd68a483cd036f38af61164e04f58ee843aedd1 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -69,22 +69,71 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sdm845_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
-               sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
-               sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
-               sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
-               sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1c8,
+               .features = VIG_SDM845_MASK_SDMA,
+               .sblk = &sdm845_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x1c8,
+               .features = VIG_SDM845_MASK_SDMA,
+               .sblk = &sdm845_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x1c8,
+               .features = VIG_SDM845_MASK_SDMA,
+               .sblk = &sdm845_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x1c8,
+               .features = VIG_SDM845_MASK_SDMA,
+               .sblk = &sdm845_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1c8,
+               .features = DMA_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1c8,
+               .features = DMA_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1c8,
+               .features = DMA_CURSOR_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x1c8,
+               .features = DMA_CURSOR_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sdm845_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index fc9adb2012a20745be61258b3283406b79d9d6ea..9c5e565842dc7951b7f7520c276846ae3d9cfa23 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm8150_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f0,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f0,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f0,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x1f0,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sm8150_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 88b577d6f0ecf05cdb2d4485ebad0da103a10713..1e7eed115e0e0d5c196989c7c75442db735a0256 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -77,22 +77,71 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sc8180x_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
-               sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x1f0,
+               .features = VIG_SDM845_MASK,
+               .sblk = &sdm845_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f0,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f0,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f0,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x1f0,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sc8180x_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 2170346376e678242fed94c3ce98b324dce5813b..23d4b59a544a8d7759e61c985d63e0c9dc049336 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm8250_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
-               sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
-               sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
-               sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
-               sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK_SDMA,
+               .sblk = &sm8250_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK_SDMA,
+               .sblk = &sm8250_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK_SDMA,
+               .sblk = &sm8250_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK_SDMA,
+               .sblk = &sm8250_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sm8250_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 277a992d51d04fff1923637ba1dbda9139053142..38225af23c0f5420da60b121ec29cdcd486e0c26 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -54,14 +54,39 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sc7180_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
-               sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sc7180_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       },
 };
 
 static const struct dpu_lm_cfg sc7180_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index e07243957963fc8e0b95655d4b27cca2c2e1c74f..356ea6144aa9c8127015290e299233907b291e4a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -42,10 +42,23 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm6115_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
-               sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm6115_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       },
 };
 
 static const struct dpu_lm_cfg sm6115_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 7779c56660388dffbb12f2c90dcdf4e4cbb9dd1a..b1b027fa16f720c98021e4c54d6ddbfb41eaaba2 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -62,14 +62,39 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm6350_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
-               sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sc7180_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       },
 };
 
 static const struct dpu_lm_cfg sm6350_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index fdbb151fbac0d8f71de1fbc5a572180789dc533c..c1181f89d6a5079a871c09b71900f716ac0f6583 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -39,10 +39,23 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
-                qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-                qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_QCM2290_MASK,
+               .sblk = &qcm2290_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &qcm2290_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       },
 };
 
 static const struct dpu_lm_cfg qcm2290_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index d8dcc9f90b81730d85e8c2631d5fe77cb4464923..1dd7771b55f884aeaee276319ee268978cc46fdf 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -43,10 +43,23 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm6375_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
-               sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm6115_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       },
 };
 
 static const struct dpu_lm_cfg sm6375_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 7b24ec5d19c4ddb12dcbba648cd0edab0e03fc1f..1515c5e09a6e18dc15947b3506a9ec5c0f70acfd 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -76,22 +76,71 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm8350_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
-               sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK,
-               sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK,
-               sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK,
-               sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x1f8,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sm8350_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 57d510d2d478e94ab60852543ae897351fa174c9..f7bd14fd82e8323311aa31f282ab0c27ab70c133 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -60,14 +60,39 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sc7280_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA,
-               sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x1f8,
+               .features = VIG_SC7280_MASK_SDMA,
+               .sblk = &sc7280_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x1f8,
+               .features = DMA_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x1f8,
+               .features = DMA_CURSOR_SDM845_MASK_SDMA,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       },
 };
 
 static const struct dpu_lm_cfg sc7280_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index dc25ef3573d27e0becaae3007f80ba8021e9480f..f532e9e5de1a7a274f5be5dfa8d796ef4835643d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
-                sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
-                sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
-                sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
-                sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
-                sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
-                sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK,
-                sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK,
-                sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x2ac,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x2ac,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x2ac,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x2ac,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x2ac,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x2ac,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x2ac,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x2ac,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sc8280xp_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 313bc055fce635006926bcf1127235fe32aa8c51..62aa7851b4cc69bb96f496429a3b72dfbbb1d049 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm8450_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK,
-               sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK,
-               sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK,
-               sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK,
-               sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x32c,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x32c,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x32c,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x32c,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8250_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x32c,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x32c,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x32c,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x32c,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       },
 };
 
 static const struct dpu_lm_cfg sm8450_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index ef9c45bb9efbeca524b34d2def386d37fa30bead..7d311fceef6ab5d3b4346ca38e1784cd9d4b9060 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -79,26 +79,87 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg sm8550_sspp[] = {
-       SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
-               sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-       SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
-               sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-       SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
-               sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-       SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
-               sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-       SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
-               sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-       SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
-               sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-       SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
-               sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-       SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
-               sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
-       SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
-               sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
-       SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
-               sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
+       {
+               .name = "sspp_0", .id = SSPP_VIG0,
+               .base = 0x4000, .len = 0x344,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8550_vig_sblk_0,
+               .xin_id = 0,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG0,
+       }, {
+               .name = "sspp_1", .id = SSPP_VIG1,
+               .base = 0x6000, .len = 0x344,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8550_vig_sblk_1,
+               .xin_id = 4,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG1,
+       }, {
+               .name = "sspp_2", .id = SSPP_VIG2,
+               .base = 0x8000, .len = 0x344,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8550_vig_sblk_2,
+               .xin_id = 8,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG2,
+       }, {
+               .name = "sspp_3", .id = SSPP_VIG3,
+               .base = 0xa000, .len = 0x344,
+               .features = VIG_SC7180_MASK,
+               .sblk = &sm8550_vig_sblk_3,
+               .xin_id = 12,
+               .type = SSPP_TYPE_VIG,
+               .clk_ctrl = DPU_CLK_CTRL_VIG3,
+       }, {
+               .name = "sspp_8", .id = SSPP_DMA0,
+               .base = 0x24000, .len = 0x344,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_0,
+               .xin_id = 1,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA0,
+       }, {
+               .name = "sspp_9", .id = SSPP_DMA1,
+               .base = 0x26000, .len = 0x344,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_1,
+               .xin_id = 5,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA1,
+       }, {
+               .name = "sspp_10", .id = SSPP_DMA2,
+               .base = 0x28000, .len = 0x344,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_2,
+               .xin_id = 9,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA2,
+       }, {
+               .name = "sspp_11", .id = SSPP_DMA3,
+               .base = 0x2a000, .len = 0x344,
+               .features = DMA_SDM845_MASK,
+               .sblk = &sdm845_dma_sblk_3,
+               .xin_id = 13,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA3,
+       }, {
+               .name = "sspp_12", .id = SSPP_DMA4,
+               .base = 0x2c000, .len = 0x344,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sm8550_dma_sblk_4,
+               .xin_id = 14,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA4,
+       }, {
+               .name = "sspp_13", .id = SSPP_DMA5,
+               .base = 0x2e000, .len = 0x344,
+               .features = DMA_CURSOR_SDM845_MASK,
+               .sblk = &sm8550_dma_sblk_5,
+               .xin_id = 15,
+               .type = SSPP_TYPE_DMA,
+               .clk_ctrl = DPU_CLK_CTRL_DMA5,
+       },
 };
 
 static const struct dpu_lm_cfg sm8550_lm[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4072a329b199a526fb239d8f2e84ca8b583cc07..d7b5a1a003512bc9ec5334b26a8943b84bfe422e 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -328,18 +328,6 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
 
-#define SSPP_BLK(_name, _id, _base, _len, _features, \
-               _sblk, _xinid, _type, _clkctrl) \
-       { \
-       .name = _name, .id = _id, \
-       .base = _base, .len = _len, \
-       .features = _features, \
-       .sblk = &_sblk, \
-       .xin_id = _xinid, \
-       .type = _type, \
-       .clk_ctrl = _clkctrl \
-       }
-
 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
                                _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);