static void
 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
-#ifdef PM8001_USE_MSIX
-       pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE, MSIX_INTERRUPT_ENABLE);
-       pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, 1);
-#else
-       pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
-       pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
-#endif
+       if (pm8001_ha->use_msix) {
+               pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE,
+                           MSIX_INTERRUPT_ENABLE);
+               pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, 1);
+       } else {
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
+       }
 }
 
 /**
 static void
 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
-#ifdef PM8001_USE_MSIX
-       pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE, MSIX_INTERRUPT_DISABLE);
-#else
-       pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
-#endif
+       if (pm8001_ha->use_msix)
+               pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE,
+                           MSIX_INTERRUPT_DISABLE);
+       else
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
 }
 
 /**
 
 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
 {
-#ifdef PM8001_USE_MSIX
-       return 1;
-#else
        u32 value;
 
+       if (pm8001_ha->use_msix)
+               return 1;
+
        value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
        if (value)
                return 1;
        return 0;
-#endif
 }
 
 /**
 
                " 4: Link rate 6.0G\n"
                " 8: Link rate 12.0G\n");
 
+bool pm8001_use_msix = true;
+module_param_named(use_msix, pm8001_use_msix, bool, 0444);
+MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
+
 static struct scsi_transport_template *pm8001_stt;
 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
 
        }
 }
 
-#ifdef PM8001_USE_MSIX
 /**
  * pm8001_setup_msix - enable MSI-X interrupt
  * @pm8001_ha: our ha struct.
 
        return rc;
 }
-#endif
 
 /**
  * pm8001_request_irq - register interrupt
 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 {
        struct pci_dev *pdev = pm8001_ha->pdev;
-#ifdef PM8001_USE_MSIX
        int rc;
 
-       if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
+       if (pm8001_use_msix && pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
                rc = pm8001_setup_msix(pm8001_ha);
                if (rc) {
                        pm8001_dbg(pm8001_ha, FAIL,
                        return rc;
                }
 
-               if (pdev->msix_cap && pci_msi_enabled())
-                       return pm8001_request_msix(pm8001_ha);
+               if (!pdev->msix_cap || !pci_msi_enabled())
+                       goto use_intx;
+
+               rc = pm8001_request_msix(pm8001_ha);
+               if (rc)
+                       return rc;
+
+               pm8001_ha->use_msix = true;
+
+               return 0;
        }
 
+use_intx:
+       /* Initialize the INT-X interrupt */
        pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
-#endif
-
-       /* initialize the INT-X interrupt */
+       pm8001_ha->use_msix = false;
        pm8001_ha->irq_vector[0].irq_id = 0;
        pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
 
 
 static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)
 {
-#ifdef PM8001_USE_MSIX
        struct pci_dev *pdev = pm8001_ha->pdev;
        int i;
 
-       for (i = 0; i < pm8001_ha->number_of_intr; i++)
-               synchronize_irq(pci_irq_vector(pdev, i));
+       if (pm8001_ha->use_msix) {
+               for (i = 0; i < pm8001_ha->number_of_intr; i++)
+                       synchronize_irq(pci_irq_vector(pdev, i));
 
-       for (i = 0; i < pm8001_ha->number_of_intr; i++)
-               free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
+               for (i = 0; i < pm8001_ha->number_of_intr; i++)
+                       free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
 
-       pci_free_irq_vectors(pdev);
-#else
+               pci_free_irq_vectors(pdev);
+               return;
+       }
+
+       /* INT-X */
        free_irq(pm8001_ha->irq, pm8001_ha->sas);
-#endif
 }
 
 /**
 
                pm8001_info(HBA, fmt, ##__VA_ARGS__);                   \
 } while (0)
 
+extern bool pm8001_use_msix;
+
 #define PM8001_USE_TASKLET
-#define PM8001_USE_MSIX
 #define PM8001_READ_VPD
 
 
        struct pm8001_device    *devices;
        struct pm8001_ccb_info  *ccb_info;
        u32                     ccb_count;
-#ifdef PM8001_USE_MSIX
+
+       bool                    use_msix;
        int                     number_of_intr;/*will be used in remove()*/
        char                    intr_drvname[PM8001_MAX_MSIX_VEC]
                                [PM8001_NAME_LENGTH+1+3+1];
-#endif
 #ifdef PM8001_USE_TASKLET
        struct tasklet_struct   tasklet[PM8001_MAX_MSIX_VEC];
 #endif
 
 static void
 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
-#ifdef PM8001_USE_MSIX
+       if (!pm8001_ha->use_msix) {
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
+               return;
+       }
+
        if (vec < 32)
                pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
        else
-               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
-                           1U << (vec - 32));
-#else
-       pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
-       pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
-#endif
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32));
 }
 
 /**
 static void
 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
-#ifdef PM8001_USE_MSIX
+       if (!pm8001_ha->use_msix) {
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
+               return;
+       }
+
        if (vec == 0xFF) {
                /* disable all vectors 0-31, 32-63 */
                pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
                pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
-       } else if (vec < 32)
+       } else if (vec < 32) {
                pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
-       else
-               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
-                           1U << (vec - 32));
-#else
-       pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
-#endif
+       } else {
+               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32));
+       }
 }
 
 /**
 
 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
 {
-#ifdef PM8001_USE_MSIX
-       return 1;
-#else
        u32 value;
 
+       if (pm8001_ha->use_msix)
+               return 1;
+
        value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
        if (value)
                return 1;
        return 0;
-#endif
 }
 
 /**