ARM: dts: vf610: ddr pinmux
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>
Fri, 19 Aug 2022 09:43:54 +0000 (11:43 +0200)
committerShawn Guo <shawnguo@kernel.org>
Sat, 3 Sep 2022 01:47:43 +0000 (09:47 +0800)
Add DDR pinmux which may be used in U-Boot after synchronising all
them device trees (and includes) from Linux.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/vf610-pinfunc.h

index 8bb970b0dff8585edc49438145b1dbfb947376fe..b7b7322a2d1bcf172e87392c10c7454d05ffb026 100644 (file)
 #define VF610_PAD_PTE28__EWM_OUT               0x214 0x000 ALT7 0x0
 #define VF610_PAD_PTA7__GPIO_134               0x218 0x000 ALT0 0x0
 #define VF610_PAD_PTA7__VIU_PIX_CLK            0x218 0x3AC ALT1 0x1
+#define VF610_PAD_DDR_RESETB                   0x21c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A15__DDR_A_15            0x220 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A14__DDR_A_14            0x224 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A13__DDR_A_13            0x228 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A12__DDR_A_12            0x22c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A11__DDR_A_11            0x230 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A10__DDR_A_10            0x234 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A9__DDR_A_9              0x238 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A8__DDR_A_8              0x23c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A7__DDR_A_7              0x240 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A6__DDR_A_6              0x244 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A5__DDR_A_5              0x248 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A4__DDR_A_4              0x24c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A3__DDR_A_3              0x250 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A2__DDR_A_2              0x254 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A1__DDR_A_1              0x258 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A0__DDR_A_0              0x25c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA2__DDR_BA_2            0x260 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA1__DDR_BA_1            0x264 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA0__DDR_BA_0            0x268 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CAS__DDR_CAS_B           0x26c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CKE__DDR_CKE_0           0x270 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CLK__DDR_CLK_0           0x274 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CS__DDR_CS_B_0           0x278 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D15__DDR_D_15            0x27c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D14__DDR_D_14            0x280 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D13__DDR_D_13            0x284 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D12__DDR_D_12            0x288 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D11__DDR_D_11            0x28c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D10__DDR_D_10            0x290 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D9__DDR_D_9              0x294 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D8__DDR_D_8              0x298 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D7__DDR_D_7              0x29c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D6__DDR_D_6              0x2a0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D5__DDR_D_5              0x2a4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D4__DDR_D_4              0x2a8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D3__DDR_D_3              0x2ac 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D2__DDR_D_2              0x2b0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D1__DDR_D_1              0x2b4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D0__DDR_D_0              0x2b8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM1__DDR_DQM_1          0x2bc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM0__DDR_DQM_0          0x2c0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS1__DDR_DQS_1          0x2c4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS0__DDR_DQS_0          0x2c8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_RAS__DDR_RAS_B           0x2cc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_WE__DDR_WE_B             0x2d0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT1__DDR_ODT_0          0x2d4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1          0x2d8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1   0x2dc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2   0x2e0 0x000 ALT0 0x0
 
 #endif