val |= EDP_PSR2_SU_SDP_SCANLINE;
 
        if (intel_dp->psr.psr2_sel_fetch_enabled) {
-               /* WA 1408330847 */
-               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-                   IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+               /* Wa_1408330847 */
+               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
                        intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
                                     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
                                     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
        intel_psr_exit(intel_dp);
        intel_psr_wait_exit_locked(intel_dp);
 
-       /* WA 1408330847 */
+       /* Wa_1408330847 */
        if (intel_dp->psr.psr2_sel_fetch_enabled &&
-           (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-            IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
                intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
                             DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);