MIPS: only register FTLBPar exception handler for supported models

Previously ExcCode 16 is unconditionally treated as the FTLB parity
exception (FTLBPar), but in fact its semantic is implementation-
dependent. Looking at various manuals it seems the FTLBPar exception is
only present on some recent MIPS Technologies cores, so only register
the handler on these.

Fixes: 75b5b5e0a262790f ("MIPS: Add support for FTLBs")
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Paul Burton <paulburton@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 724dfddcab92d7bf2e66c31a9afbe93ba251bbb3..0b1bc7ed913b20a1d5345d44dc83108d57e3e7b0 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -568,6 +568,10 @@
 # define cpu_has_mac2008_only  __opt(MIPS_CPU_MAC_2008_ONLY)
 #endif
 
+#ifndef cpu_has_ftlbparex
+# define cpu_has_ftlbparex     __opt(MIPS_CPU_FTLBPAREX)
+#endif
+
 #ifdef CONFIG_SMP
 /*
  * Some systems share FTLB RAMs between threads within a core (siblings in

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f5b04e8f60619dff2340d9307de81c83023d8445..9d08bd33b11f71abfee53d76b46c9f8c656f4ded 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -427,6 +427,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_MM_SYSAD      BIT_ULL(58)     /* CPU supports write-through SysAD Valid merge */
 #define MIPS_CPU_MM_FULL       BIT_ULL(59)     /* CPU supports write-through full merge */
 #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60)     /* CPU Only support MAC2008 Fused multiply-add instruction */
+#define MIPS_CPU_FTLBPAREX     BIT_ULL(61)     /* CPU has FTLB parity exception */
 
 /*
  * CPU ASE encodings

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d9e8d39a7289bea6958cb7b0df904d1c1ce5612d..519d101fd00903ca046f1056be87a81bc29ddcbe 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1827,6 +1827,19 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
        default:
                break;
        }
+
+       /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
+        * cache/FTLB parity exceptions.
+        */
+       switch (__get_cpu_type(c->cputype)) {
+       case CPU_PROAPTIV:
+       case CPU_P5600:
+       case CPU_P6600:
+       case CPU_I6400:
+       case CPU_I6500:
+               c->options |= MIPS_CPU_FTLBPAREX;
+               break;
+       }
 }
 
 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 06aba49d37c90421dc4bd48b4a24eaa9ede144cc..9c37a69972596ec44caebc52fa7ace3a17a39bc1 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2454,7 +2454,8 @@ void __init trap_init(void)
        if (cpu_has_fpu && !cpu_has_nofpuex)
                set_except_vector(EXCCODE_FPE, handle_fpe);
 
-       set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
+       if (cpu_has_ftlbparex)
+               set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
 
        if (cpu_has_rixiex) {
                set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);