arm64: tegra: Fixup pinmux node names
authorThierry Reding <treding@nvidia.com>
Fri, 4 Nov 2022 12:35:08 +0000 (13:35 +0100)
committerThierry Reding <treding@nvidia.com>
Mon, 21 Nov 2022 12:30:15 +0000 (13:30 +0100)
Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.

Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
arch/arm64/boot/dts/nvidia/tegra194.dtsi
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
arch/arm64/boot/dts/nvidia/tegra210.dtsi

index d461da0b80492ff9bf09c76c87ac3895aa991fd9..3e8dee85d55f25e3ed9f32776adf58e9933efe5e 100644 (file)
@@ -62,7 +62,7 @@
                pinctrl-names = "default";
                pinctrl-0 = <&pinmux_default>;
 
-               pinmux_default: pinmux@0 {
+               pinmux_default: pinmux {
                        dap_mclk1_pw4 {
                                nvidia,pins = "dap_mclk1_pw4";
                                nvidia,function = "extperiph1";
index 81a2ab56810f1e96d204ee2e4a8fd5ee3dd70224..4afcbd60e144e9d3be4c72484d20f3e059eebf4e 100644 (file)
                        reg = <0x2430000 0x17000>;
                        status = "okay";
 
-                       pex_rst_c5_out_state: pex_rst_c5_out {
+                       pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
                                pex_rst {
                                        nvidia,pins = "pex_l5_rst_n_pgg1";
                                        nvidia,schmitt = <TEGRA_PIN_DISABLE>;
                                };
                        };
 
-                       clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
+                       clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir {
                                clkreq {
                                        nvidia,pins = "pex_l5_clkreq_n_pgg0";
                                        nvidia,schmitt = <TEGRA_PIN_DISABLE>;
index 4286e04e685ca793d3c17d30408966a40faac26f..dd9a17922fe5cea2f4bf74ff27cd8ce0bb331008 100644 (file)
                        };
                };
 
-               dvfs_pwm_active_state: dvfs_pwm_active {
+               dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
                        dvfs_pwm_pbb1 {
                                nvidia,pins = "dvfs_pwm_pbb1";
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                        };
                };
 
-               dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+               dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
                        dvfs_pwm_pbb1 {
                                nvidia,pins = "dvfs_pwm_pbb1";
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
index 37678c337a34cb86f51981ffaf20166075da5797..2041371ea7ff8e3b4cbb846def3e4de8591e2b5b 100644 (file)
        };
 
        pinmux@700008d4 {
-               dvfs_pwm_active_state: dvfs_pwm_active {
+               dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
                        dvfs_pwm_pbb1 {
                                nvidia,pins = "dvfs_pwm_pbb1";
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                        };
                };
 
-               dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+               dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
                        dvfs_pwm_pbb1 {
                                nvidia,pins = "dvfs_pwm_pbb1";
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
index e2d84335ec82f03d04b1cf795ca39943b4a59436..92c03ef623da92e93e33ced7fa80c72e5851de2a 100644 (file)
                compatible = "nvidia,tegra210-pinmux";
                reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
                      <0x0 0x70003000 0x0 0x294>; /* Mux registers */
-               sdmmc1_3v3_drv: sdmmc1-3v3-drv {
+
+               sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
                        sdmmc1 {
                                nvidia,pins = "drive_sdmmc1";
                                nvidia,pull-down-strength = <0x8>;
                                nvidia,pull-up-strength = <0x8>;
                        };
                };
-               sdmmc1_1v8_drv: sdmmc1-1v8-drv {
+
+               sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
                        sdmmc1 {
                                nvidia,pins = "drive_sdmmc1";
                                nvidia,pull-down-strength = <0x4>;
                                nvidia,pull-up-strength = <0x3>;
                        };
                };
-               sdmmc2_1v8_drv: sdmmc2-1v8-drv {
+
+               sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {
                        sdmmc2 {
                                nvidia,pins = "drive_sdmmc2";
                                nvidia,pull-down-strength = <0x10>;
                                nvidia,pull-up-strength = <0x10>;
                        };
                };
-               sdmmc3_3v3_drv: sdmmc3-3v3-drv {
+
+               sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
                        sdmmc3 {
                                nvidia,pins = "drive_sdmmc3";
                                nvidia,pull-down-strength = <0x8>;
                                nvidia,pull-up-strength = <0x8>;
                        };
                };
-               sdmmc3_1v8_drv: sdmmc3-1v8-drv {
+
+               sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
                        sdmmc3 {
                                nvidia,pins = "drive_sdmmc3";
                                nvidia,pull-down-strength = <0x4>;
                                nvidia,pull-up-strength = <0x3>;
                        };
                };
-               sdmmc4_1v8_drv: sdmmc4-1v8-drv {
+
+               sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {
                        sdmmc4 {
                                nvidia,pins = "drive_sdmmc4";
                                nvidia,pull-down-strength = <0x10>;