i40e: use 16B HW descriptors instead of 32B
authorBjörn Töpel <bjorn.topel@intel.com>
Tue, 25 Aug 2020 11:35:55 +0000 (13:35 +0200)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Mon, 14 Sep 2020 16:45:35 +0000 (09:45 -0700)
The i40e NIC supports two flavors of HW descriptors, 16 and 32
byte. The latter has, obviously, room for more offloading
information. However, the only fields of the 32B HW descriptor that is
being used by the driver, is also available in the 16B descriptor.

In other words; Reading and writing 32 bytes instead of 16 byte is a
waste of bus bandwidth.

This commit starts using 16 byte descriptors instead of 32 byte
descriptors.

For AF_XDP the rx_drop benchmark was improved by 2%.

Signed-off-by: Björn Töpel <bjorn.topel@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/i40e/i40e.h
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
drivers/net/ethernet/intel/i40e/i40e_main.c
drivers/net/ethernet/intel/i40e/i40e_trace.h
drivers/net/ethernet/intel/i40e/i40e_txrx.c
drivers/net/ethernet/intel/i40e/i40e_txrx.h
drivers/net/ethernet/intel/i40e/i40e_type.h

index a7e212d1caa2226ad4d9ef2b43568e454a74b949..ada0e93c38f04fca14f0ea717068a9971ef91a44 100644 (file)
@@ -90,7 +90,7 @@
 #define I40E_OEM_RELEASE_MASK          0x0000ffff
 
 #define I40E_RX_DESC(R, i)     \
-       (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
+       (&(((union i40e_rx_desc *)((R)->desc))[i]))
 #define I40E_TX_DESC(R, i)     \
        (&(((struct i40e_tx_desc *)((R)->desc))[i]))
 #define I40E_TX_CTXTDESC(R, i) \
index d3ad2e3aa8383555cad76b9c2e36688ce799ad69..d7c13ca9be7dd8f258415b240c6af86db7db4c59 100644 (file)
@@ -604,10 +604,9 @@ static void i40e_dbg_dump_desc(int cnt, int vsi_seid, int ring_id, int desc_n,
                        } else {
                                rxd = I40E_RX_DESC(ring, i);
                                dev_info(&pf->pdev->dev,
-                                        "   d[%03x] = 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n",
+                                        "   d[%03x] = 0x%016llx 0x%016llx\n",
                                         i, rxd->read.pkt_addr,
-                                        rxd->read.hdr_addr,
-                                        rxd->read.rsvd1, rxd->read.rsvd2);
+                                        rxd->read.hdr_addr);
                        }
                }
        } else if (cnt == 3) {
@@ -625,10 +624,9 @@ static void i40e_dbg_dump_desc(int cnt, int vsi_seid, int ring_id, int desc_n,
                } else {
                        rxd = I40E_RX_DESC(ring, desc_n);
                        dev_info(&pf->pdev->dev,
-                                "vsi = %02i rx ring = %02i d[%03x] = 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n",
+                                "vsi = %02i rx ring = %02i d[%03x] = 0x%016llx 0x%016llx\n",
                                 vsi_seid, ring_id, desc_n,
-                                rxd->read.pkt_addr, rxd->read.hdr_addr,
-                                rxd->read.rsvd1, rxd->read.rsvd2);
+                                rxd->read.pkt_addr, rxd->read.hdr_addr);
                }
        } else {
                dev_info(&pf->pdev->dev, "dump desc rx/tx/xdp <vsi_seid> <ring_id> [<desc_n>]\n");
index 9cfaa99da4e60588b45fbc4b42c431750a27637b..07207e21874f137d6ca4949eb8c59863bdeeb091 100644 (file)
@@ -3321,8 +3321,8 @@ static int i40e_configure_rx_ring(struct i40e_ring *ring)
        rx_ctx.base = (ring->dma / 128);
        rx_ctx.qlen = ring->count;
 
-       /* use 32 byte descriptors */
-       rx_ctx.dsize = 1;
+       /* use 16 byte descriptors */
+       rx_ctx.dsize = 0;
 
        /* descriptor type is always zero
         * rx_ctx.dtype = 0;
index 424f02077e2e24b016a9b4f2c28da228f28910ee..983f8b98b2756e37e456f15c463d88b41a956cdb 100644 (file)
@@ -112,7 +112,7 @@ DECLARE_EVENT_CLASS(
        i40e_rx_template,
 
        TP_PROTO(struct i40e_ring *ring,
-                union i40e_32byte_rx_desc *desc,
+                union i40e_16byte_rx_desc *desc,
                 struct sk_buff *skb),
 
        TP_ARGS(ring, desc, skb),
@@ -140,7 +140,7 @@ DECLARE_EVENT_CLASS(
 DEFINE_EVENT(
        i40e_rx_template, i40e_clean_rx_irq,
        TP_PROTO(struct i40e_ring *ring,
-                union i40e_32byte_rx_desc *desc,
+                union i40e_16byte_rx_desc *desc,
                 struct sk_buff *skb),
 
        TP_ARGS(ring, desc, skb));
@@ -148,7 +148,7 @@ DEFINE_EVENT(
 DEFINE_EVENT(
        i40e_rx_template, i40e_clean_rx_irq_rx,
        TP_PROTO(struct i40e_ring *ring,
-                union i40e_32byte_rx_desc *desc,
+                union i40e_16byte_rx_desc *desc,
                 struct sk_buff *skb),
 
        TP_ARGS(ring, desc, skb));
index b43bc20f701d62cfdc367233c18a16c50e1038da..1606ba5318f7276223e7199498aa3f2570754276 100644 (file)
@@ -533,11 +533,11 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
 {
        struct i40e_pf *pf = rx_ring->vsi->back;
        struct pci_dev *pdev = pf->pdev;
-       struct i40e_32b_rx_wb_qw0 *qw0;
+       struct i40e_16b_rx_wb_qw0 *qw0;
        u32 fcnt_prog, fcnt_avail;
        u32 error;
 
-       qw0 = (struct i40e_32b_rx_wb_qw0 *)&qword0_raw;
+       qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw;
        error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
                I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 
@@ -1418,7 +1418,7 @@ int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
        u64_stats_init(&rx_ring->syncp);
 
        /* Round up to nearest 4K */
-       rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
+       rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc);
        rx_ring->size = ALIGN(rx_ring->size, 4096);
        rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
                                           &rx_ring->dma, GFP_KERNEL);
index 703b644fd71f7e36fa95c346851ad6d98458c49a..66c2b92c0d10056ae7f93443cf23e66832103ba0 100644 (file)
@@ -110,7 +110,7 @@ enum i40e_dyn_idx_t {
  */
 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256
 #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
-#define i40e_rx_desc i40e_32byte_rx_desc
+#define i40e_rx_desc i40e_16byte_rx_desc
 
 #define I40E_RX_DMA_ATTR \
        (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
index 52410d609ba1d2770ab589abb8121d5917c4ea7f..97d29df65f9e87b93a51b9a6f6d6dcbffa351a86 100644 (file)
@@ -628,7 +628,7 @@ union i40e_16byte_rx_desc {
                __le64 hdr_addr; /* Header buffer address */
        } read;
        struct {
-               struct {
+               struct i40e_16b_rx_wb_qw0 {
                        struct {
                                union {
                                        __le16 mirroring_status;
@@ -647,6 +647,9 @@ union i40e_16byte_rx_desc {
                        __le64 status_error_len;
                } qword1;
        } wb;  /* writeback */
+       struct {
+               u64 qword[2];
+       } raw;
 };
 
 union i40e_32byte_rx_desc {