arm64: dts: hi3798cv200: add GICH, GICV register space and irq

This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240219-cache-v3-2-a33c57534ae9@outlook.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index d01023401d7e3fb31c0424509bd6999e6882f843..fc64d2fa99eb11d510ed323d8bab057edbb9c0a8 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,11 @@
        gic: interrupt-controller@f1001000 {
                compatible = "arm,gic-400";
                reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
-                     <0x0 0xf1002000 0x0 0x2000>;  /* GICC */
+                     <0x0 0xf1002000 0x0 0x2000>,  /* GICC */
+                     <0x0 0xf1004000 0x0 0x2000>,  /* GICH */
+                     <0x0 0xf1006000 0x0 0x2000>;  /* GICV */
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_HIGH)>;
                #address-cells = <0>;
                #interrupt-cells = <3>;
                interrupt-controller;