ARM: dts: qcom: sdx55: Add support for SDHCI controller

Add devicetree support for SDHCI controller found in Qualcomm SDX55
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.
Hence, the support is added by reusing the existing sdhci driver with
"qcom,sdhci-msm-v5" as the fallback.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210106125322.61840-5-manivannan.sadhasivam@linaro.org
[bjorn: added include of qcom,gcc-sdx55.h]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 3698c2f294816e2b593a2972d51f4d03aed716d6..781a4ec83d47810a7f4b7fc33fb8c4324949642c 100644 (file)
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -6,6 +6,7 @@
  * Copyright (c) 2020, Linaro Ltd.
  */
 
+#include <dt-bindings/clock/qcom,gcc-sdx55.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -130,6 +131,18 @@
                        status = "disabled";
                };
 
+               sdhc_1: sdhci@8804000 {
+                       compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
+                       reg = <0x08804000 0x1000>;
+                       interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>;
+                       clock-names = "iface", "core";
+                       status = "disabled";
+               };
+
                pdc: interrupt-controller@b210000 {
                        compatible = "qcom,sdx55-pdc", "qcom,pdc";
                        reg = <0x0b210000 0x30000>;