PCI/PM: Write 0 to PMCSR in pci_power_up() in all cases
authorRafael J. Wysocki <rafael.j.wysocki@intel.com>
Thu, 5 May 2022 18:10:43 +0000 (20:10 +0200)
committerBjorn Helgaas <bhelgaas@google.com>
Thu, 5 May 2022 19:19:49 +0000 (14:19 -0500)
Make pci_power_up() write 0 to the device's PCI_PM_CTRL register in
order to put it into D0 regardless of the power state returned by
the previous read from that register which should not matter.

Link: https://lore.kernel.org/r/5748066.MhkbZ0Pkbq@kreacher
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/pci.c

index a5b93f85377abba5453bfd0b0357e9297f7dd0d5..5cce2cae093393504abb2fc1050ea3260a657c75 100644 (file)
@@ -1230,15 +1230,10 @@ int pci_power_up(struct pci_dev *dev)
        }
 
        /*
-        * If we're (effectively) in D3, force entire word to 0. This doesn't
-        * affect PME_Status, disables PME_En, and sets PowerState to 0.
+        * Force the entire word to 0. This doesn't affect PME_Status, disables
+        * PME_En, and sets PowerState to 0.
         */
-       if (state == PCI_D3hot)
-               pmcsr = 0;
-       else
-               pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
-
-       pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
+       pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
 
        /* Mandatory transition delays; see PCI PM 1.2. */
        if (state == PCI_D3hot)