tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
 
        /* Set the control register bits */
-       ctrl = CNTRLREG_STEPCONFIGWRT |
-                       CNTRLREG_STEPID;
-       if (tsc_wires > 0)
-               ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
+       ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
        tscadc_writel(tscadc, REG_CTRL, ctrl);
 
        /* Set register bits for Idle Config Mode */
-       if (tsc_wires > 0)
+       if (tsc_wires > 0) {
+               tscadc->tsc_wires = tsc_wires;
+               if (tsc_wires == 5)
+                       ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
+               else
+                       ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
                tscadc_idle_config(tscadc);
+       }
 
        /* Enable the TSC module enable bit */
-       ctrl = tscadc_readl(tscadc, REG_CTRL);
        ctrl |= CNTRLREG_TSCSSENB;
        tscadc_writel(tscadc, REG_CTRL, ctrl);
 
 static int tscadc_resume(struct device *dev)
 {
        struct ti_tscadc_dev    *tscadc_dev = dev_get_drvdata(dev);
-       unsigned int restore, ctrl;
+       u32 ctrl;
 
        pm_runtime_get_sync(dev);
 
        /* context restore */
        ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
-       if (tscadc_dev->tsc_cell != -1)
-               ctrl |= CNTRLREG_TSCENB | CNTRLREG_4WIRE;
        tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
 
-       if (tscadc_dev->tsc_cell != -1)
+       if (tscadc_dev->tsc_cell != -1) {
+               if (tscadc_dev->tsc_wires == 5)
+                       ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
+               else
+                       ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
                tscadc_idle_config(tscadc_dev);
-       restore = tscadc_readl(tscadc_dev, REG_CTRL);
-       tscadc_writel(tscadc_dev, REG_CTRL,
-                       (restore | CNTRLREG_TSCSSENB));
+       }
+       ctrl |= CNTRLREG_TSCSSENB;
+       tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
 
        tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);