static void write_response_pdma_cb(ESPState *s)
{
esp_set_phase(s, STAT_ST);
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
if (s->dma_memory_write) {
s->dma_memory_write(s->dma_opaque, buf, 2);
esp_set_phase(s, STAT_ST);
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
} else {
static void esp_dma_done(ESPState *s)
{
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RINTR] |= INTR_BS;
s->rregs[ESP_RFLAGS] = 0;
- esp_set_tc(s, 0);
esp_raise_irq(s);
}
*/
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
esp_set_phase(s, STAT_CD);
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RSEQ] = SEQ_CD;
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
*/
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
esp_set_phase(s, STAT_CD);
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RSEQ] = SEQ_CD;
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
*/
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
esp_set_phase(s, STAT_CD);
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RSEQ] = SEQ_CD;
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
* completion interrupt
*/
s->data_in_ready = true;
- s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
}
if (s->dma) {
dmalen = esp_get_tc(s);
trace_esp_handle_ti(dmalen);
- s->rregs[ESP_RSTAT] &= ~STAT_TC;
esp_do_dma(s);
} else {
trace_esp_handle_ti(s->ti_size);
* of the FIFO so switch to status phase
*/
esp_set_phase(s, STAT_ST);
- s->rregs[ESP_RSTAT] |= STAT_TC;
}
}
s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo);