clk: qcom: ipq8074: Add missing clocks for pcie

Add missing clocks and resets for pcie port0 of ipq8074 devices.

Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1593940680-2363-5-git-send-email-sivaprak@codeaurora.org
[sboyd@kernel.org: Make freq table static const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index e01f5f591d1e2507846b966b8a4768504068ec54..ef2c9c4cf9abb664a356588e10af34e2cea14484 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4316,6 +4316,62 @@ static struct clk_branch gcc_gp3_clk = {
        },
 };
 
+static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(100000000, P_GPLL0, 8, 0, 0),
+       { }
+};
+
+struct clk_rcg2 pcie0_rchng_clk_src = {
+       .cmd_rcgr = 0x75070,
+       .freq_tbl = ftbl_pcie_rchng_clk_src,
+       .hid_width = 5,
+       .parent_map = gcc_xo_gpll0_map,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "pcie0_rchng_clk_src",
+               .parent_hws = (const struct clk_hw *[]) {
+                               &gpll0.clkr.hw },
+               .num_parents = 2,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_branch gcc_pcie0_rchng_clk = {
+       .halt_reg = 0x75070,
+       .halt_bit = 31,
+       .clkr = {
+               .enable_reg = 0x75070,
+               .enable_mask = BIT(1),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie0_rchng_clk",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &pcie0_rchng_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+       .halt_reg = 0x75048,
+       .halt_bit = 31,
+       .clkr = {
+               .enable_reg = 0x75048,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie0_axi_s_bridge_clk",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &pcie0_axi_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_hw *gcc_ipq8074_hws[] = {
        &gpll0_out_main_div2.hw,
        &gpll6_out_main_div2.hw,
@@ -4551,6 +4607,9 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+       [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
+       [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
+       [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -4678,6 +4737,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
        [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
        [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
        [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+       [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
        [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
        [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
        [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },