cpufreq: qcom-nvmem: Add MSM8909

When the MSM8909 SoC is used together with the PM8909 PMIC the primary
power supply for the CPU (VDD_APC) is shared with other components to
the SoC, namely the VDD_CX power domain typically supplied by the PM8909
S1 regulator. This means that all votes for necessary performance states
go via the RPM firmware which collects the requirements from all the
processors in the SoC. The RPM firmware then chooses the actual voltage
based on the performance states ("corners"), depending on calibration
values in the NVMEM and other factors.

The MSM8909 SoC is also sometimes used with the PM8916 or PM660 PMIC.
In that case there is a dedicated regulator connected to VDD_APC and
Linux is responsible to do adaptive voltage scaling using CPR (similar
to the existing code for QCS404).

This difference can be described in the device tree, by either assigning
the CPU a power domain from RPMPD or from the CPR driver.

Describe this using "perf" as generic power domain name, which is also
used already for SCMI based platforms.

Also add a simple function that reads the speedbin from a NVMEM cell
and sets it as-is for opp-supported-hw. The actual bit position can be
described in the device tree without additional driver changes.

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[ Viresh: Fixed rebase conflict. ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 03586fee15aacd95ef4acdd435173cffcabdee32..301640dec189af9f3008e72d26129ae31cd3b17c 100644 (file)
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -52,6 +52,24 @@ struct qcom_cpufreq_drv {
 
 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
+static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
+                                          struct nvmem_cell *speedbin_nvmem,
+                                          char **pvs_name,
+                                          struct qcom_cpufreq_drv *drv)
+{
+       u8 *speedbin;
+
+       *pvs_name = NULL;
+       speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
+       if (IS_ERR(speedbin))
+               return PTR_ERR(speedbin);
+
+       dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin);
+       drv->versions = 1 << *speedbin;
+       kfree(speedbin);
+       return 0;
+}
+
 static void get_krait_bin_format_a(struct device *cpu_dev,
                                          int *speed, int *pvs, int *pvs_ver,
                                          u8 *buf)
@@ -207,6 +225,8 @@ len_error:
        return ret;
 }
 
+static const char *generic_genpd_names[] = { "perf", NULL };
+
 static const struct qcom_cpufreq_match_data match_data_kryo = {
        .get_version = qcom_cpufreq_kryo_name_version,
 };
@@ -215,6 +235,11 @@ static const struct qcom_cpufreq_match_data match_data_krait = {
        .get_version = qcom_cpufreq_krait_name_version,
 };
 
+static const struct qcom_cpufreq_match_data match_data_msm8909 = {
+       .get_version = qcom_cpufreq_simple_get_version,
+       .genpd_names = generic_genpd_names,
+};
+
 static const char *qcs404_genpd_names[] = { "cpr", NULL };
 
 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
@@ -344,6 +369,7 @@ static struct platform_driver qcom_cpufreq_driver = {
 
 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
        { .compatible = "qcom,apq8096", .data = &match_data_kryo },
+       { .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
        { .compatible = "qcom,msm8996", .data = &match_data_kryo },
        { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
        { .compatible = "qcom,ipq8064", .data = &match_data_krait },