for (i = 0; i < 4; i++) {
if (stat & TSI148_LCSR_INTS_MBS[i]) {
val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
- dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
- ": 0x%x\n", i, val);
+ dev_err(tsi148_bridge->parent, "VME Mailbox %d received: 0x%x\n",
+ i, val);
serviced |= TSI148_LCSR_INTC_MBC[i];
}
}
bridge = tsi148_bridge->driver_priv;
- dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
- "attributes: %08x\n",
+ dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n",
ioread32be(bridge->base + TSI148_LCSR_EDPAU),
ioread32be(bridge->base + TSI148_LCSR_EDPAL),
ioread32be(bridge->base + TSI148_LCSR_EDPAT));
- dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
- "completion reg: %08x\n",
+ dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n",
ioread32be(bridge->base + TSI148_LCSR_EDPXA),
ioread32be(bridge->base + TSI148_LCSR_EDPXS));
reg_join(error_addr_high, error_addr_low, &error_addr);
/* Check for exception register overflow (we have lost error data) */
- if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
- dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
- "Occurred\n");
- }
+ if (error_attrib & TSI148_LCSR_VEAT_VEOF)
+ dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow Occurred\n");
if (err_chk)
vme_bus_error_handler(tsi148_bridge, error_addr, error_am);
IRQF_SHARED,
driver_name, tsi148_bridge);
if (result) {
- dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
- "vector %02X\n", pdev->irq);
+ dev_err(tsi148_bridge->parent, "Can't get assigned pci irq vector %02X\n",
+ pdev->irq);
return result;
}
return -EINVAL;
}
if (pci_offset_low & (granularity - 1)) {
- dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
- "alignment\n");
+ dev_err(tsi148_bridge->parent, "Invalid PCI Offset alignment\n");
return -EINVAL;
}
temp_ctl &= ~0xF;
if (cycle & VME_SUPER)
- temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
+ temp_ctl |= TSI148_LCSR_ITAT_SUPR;
if (cycle & VME_USER)
temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
if (cycle & VME_PROG)
&image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
0, NULL, NULL);
if (retval) {
- dev_err(tsi148_bridge->parent, "Failed to allocate mem "
- "resource for window %d size 0x%lx start 0x%lx\n",
+ dev_err(tsi148_bridge->parent, "Failed to allocate mem resource for window %d size 0x%lx start 0x%lx\n",
image->number, (unsigned long)size,
(unsigned long)image->bus_resource.start);
goto err_resource;
/* Verify input data */
if (vme_base & 0xFFFF) {
- dev_err(tsi148_bridge->parent, "Invalid VME Window "
- "alignment\n");
+ dev_err(tsi148_bridge->parent, "Invalid VME Window alignment\n");
retval = -EINVAL;
goto err_window;
}
if ((size == 0) && (enabled != 0)) {
- dev_err(tsi148_bridge->parent, "Size must be non-zero for "
- "enabled windows\n");
+ dev_err(tsi148_bridge->parent, "Size must be non-zero for enabled windows\n");
retval = -EINVAL;
goto err_window;
}
retval = tsi148_alloc_resource(image, size);
if (retval) {
spin_unlock(&image->lock);
- dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
- "resource\n");
+ dev_err(tsi148_bridge->parent, "Unable to allocate memory for resource\n");
goto err_res;
}
}
if (vme_offset_low & 0xFFFF) {
spin_unlock(&image->lock);
- dev_err(tsi148_bridge->parent, "Invalid VME Offset "
- "alignment\n");
+ dev_err(tsi148_bridge->parent, "Invalid VME Offset alignment\n");
retval = -EINVAL;
goto err_gran;
}
temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
}
if (cycle & VME_2eSSTB) {
- dev_warn(tsi148_bridge->parent, "Currently not setting "
- "Broadcast Select Registers\n");
+ dev_warn(tsi148_bridge->parent, "Currently not setting Broadcast Select Registers\n");
temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
}
val |= TSI148_LCSR_DSAT_TM_2eSST;
if (cycle & VME_2eSSTB) {
- dev_err(dev, "Currently not setting Broadcast Select "
- "Registers\n");
+ dev_err(dev, "Currently not setting Broadcast Select Registers\n");
val |= TSI148_LCSR_DSAT_TM_2eSSTB;
}
val |= TSI148_LCSR_DDAT_TM_2eSST;
if (cycle & VME_2eSSTB) {
- dev_err(dev, "Currently not setting Broadcast Select "
- "Registers\n");
+ dev_err(dev, "Currently not setting Broadcast Select Registers\n");
val |= TSI148_LCSR_DDAT_TM_2eSSTB;
}
/* Test descriptor alignment */
if ((unsigned long)&entry->descriptor & 0x7) {
- dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
- "byte boundary as required: %p\n",
+ dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 byte boundary as required: %p\n",
&entry->descriptor);
retval = -EINVAL;
goto err_align;
/* Need to add to pending here */
mutex_unlock(&ctrlr->mtx);
return -EBUSY;
- } else {
- list_add(&list->list, &ctrlr->running);
}
+ list_add(&list->list, &ctrlr->running);
+
/* Get first bus address and write into registers */
entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
list);
for (i = 0; i < lm->monitors; i++) {
if (bridge->lm_callback[i]) {
mutex_unlock(&lm->mtx);
- dev_err(tsi148_bridge->parent, "Location monitor "
- "callback attached, can't reset\n");
+ dev_err(tsi148_bridge->parent, "Location monitor callback attached, can't reset\n");
return -EBUSY;
}
}
}
if (cycle & VME_SUPER)
- lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
+ lm_ctl |= TSI148_LCSR_LMAT_SUPR;
if (cycle & VME_USER)
lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
if (cycle & VME_PROG)
lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
mutex_unlock(&lm->mtx);
- dev_err(tsi148_bridge->parent, "Location monitor not properly "
- "configured\n");
+ dev_err(tsi148_bridge->parent, "Location monitor not properly configured\n");
return -EINVAL;
}
VME_CRCSR_BUF_SIZE,
&bridge->crcsr_bus, GFP_KERNEL);
if (!bridge->crcsr_kernel) {
- dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
- "CR/CSR image\n");
+ dev_err(tsi148_bridge->parent, "Failed to allocate memory for CR/CSR image\n");
return -ENOMEM;
}
(vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
VME_D16);
if (retval)
- dev_err(tsi148_bridge->parent, "Configuring flush image"
- " failed\n");
+ dev_err(tsi148_bridge->parent, "Configuring flush image failed\n");
}
return 0;