drm/xe: Add XE_BO_NEEDS_UC flag to force UC mode instead WB

When we map BO in GGTT, then by default we are using PAT index
that corresponds to XE_CACHE_WB but ppcoming feature will require
use of the PAT index of the XE_CACHE_UC.  Define new BO flag that
could be used during BO creation to force alternate caching.

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-7-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 9b1279aca1272cd69eab6d1121ed651b83210166..97b32528c600f6c612828e1fac872ac28a9b4017 100644 (file)
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -44,6 +44,7 @@
 #define XE_BO_FIXED_PLACEMENT_BIT      BIT(11)
 #define XE_BO_PAGETABLE                        BIT(12)
 #define XE_BO_NEEDS_CPU_ACCESS         BIT(13)
+#define XE_BO_NEEDS_UC                 BIT(14)
 /* this one is trigger internally only */
 #define XE_BO_INTERNAL_TEST            BIT(30)
 #define XE_BO_INTERNAL_64K             BIT(31)

diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 3efd2d066bf723c6ef7378523516d0048172a32e..c639dbf3bdd27bc08a722d713453e8a34221492b 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -334,7 +334,8 @@ int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,
 
 void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
 {
-       u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];
+       u16 cache_mode = bo->flags & XE_BO_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB;
+       u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode];
        u64 start = bo->ggtt_node.start;
        u64 offset, pte;