writel((__force u32)cpu_to_be32(temp_mac[1]),
               fep->hwp + FEC_ADDR_HIGH);
 
-       /* Clear any outstanding interrupt. */
-       writel(0xffffffff, fep->hwp + FEC_IEVENT);
+       /* Clear any outstanding interrupt, except MDIO. */
+       writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
 
        fec_enet_bd_init(ndev);
 
        if (fep->link)
                writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
        else
-               writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
+               writel(0, fep->hwp + FEC_IMASK);
 
        /* Init the interrupt coalescing */
        fec_enet_itr_coal_init(ndev);
        irqreturn_t ret = IRQ_NONE;
 
        int_events = readl(fep->hwp + FEC_IEVENT);
+
+       /* Don't clear MDIO events, we poll for those */
+       int_events &= ~FEC_ENET_MII;
+
        writel(int_events, fep->hwp + FEC_IEVENT);
        fec_enet_collect_events(fep, int_events);
 
                ret = IRQ_HANDLED;
 
                if (napi_schedule_prep(&fep->napi)) {
-                       /* Disable the NAPI interrupts */
-                       writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
+                       /* Disable interrupts */
+                       writel(0, fep->hwp + FEC_IMASK);
                        __napi_schedule(&fep->napi);
                }
        }
 
-       if (int_events & FEC_ENET_MII) {
-               ret = IRQ_HANDLED;
-               complete(&fep->mdio_done);
-       }
        return ret;
 }
 
                phy_print_status(phy_dev);
 }
 
+static int fec_enet_mdio_wait(struct fec_enet_private *fep)
+{
+       uint ievent;
+       int ret;
+
+       ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
+                                       ievent & FEC_ENET_MII, 2, 30000);
+
+       if (!ret)
+               writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
+
+       return ret;
+}
+
 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 {
        struct fec_enet_private *fep = bus->priv;
        struct device *dev = &fep->pdev->dev;
-       unsigned long time_left;
        int ret = 0, frame_start, frame_addr, frame_op;
        bool is_c45 = !!(regnum & MII_ADDR_C45);
 
        if (ret < 0)
                return ret;
 
-       reinit_completion(&fep->mdio_done);
-
        if (is_c45) {
                frame_start = FEC_MMFR_ST_C45;
 
                       fep->hwp + FEC_MII_DATA);
 
                /* wait for end of transfer */
-               time_left = wait_for_completion_timeout(&fep->mdio_done,
-                               usecs_to_jiffies(FEC_MII_TIMEOUT));
-               if (time_left == 0) {
+               ret = fec_enet_mdio_wait(fep);
+               if (ret) {
                        netdev_err(fep->netdev, "MDIO address write timeout\n");
-                       ret = -ETIMEDOUT;
                        goto out;
                }
 
                FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
 
        /* wait for end of transfer */
-       time_left = wait_for_completion_timeout(&fep->mdio_done,
-                       usecs_to_jiffies(FEC_MII_TIMEOUT));
-       if (time_left == 0) {
+       ret = fec_enet_mdio_wait(fep);
+       if (ret) {
                netdev_err(fep->netdev, "MDIO read timeout\n");
-               ret = -ETIMEDOUT;
                goto out;
        }
 
 {
        struct fec_enet_private *fep = bus->priv;
        struct device *dev = &fep->pdev->dev;
-       unsigned long time_left;
        int ret, frame_start, frame_addr;
        bool is_c45 = !!(regnum & MII_ADDR_C45);
 
        else
                ret = 0;
 
-       reinit_completion(&fep->mdio_done);
-
        if (is_c45) {
                frame_start = FEC_MMFR_ST_C45;
 
                       fep->hwp + FEC_MII_DATA);
 
                /* wait for end of transfer */
-               time_left = wait_for_completion_timeout(&fep->mdio_done,
-                       usecs_to_jiffies(FEC_MII_TIMEOUT));
-               if (time_left == 0) {
+               ret = fec_enet_mdio_wait(fep);
+               if (ret) {
                        netdev_err(fep->netdev, "MDIO address write timeout\n");
-                       ret = -ETIMEDOUT;
                        goto out;
                }
        } else {
                fep->hwp + FEC_MII_DATA);
 
        /* wait for end of transfer */
-       time_left = wait_for_completion_timeout(&fep->mdio_done,
-                       usecs_to_jiffies(FEC_MII_TIMEOUT));
-       if (time_left == 0) {
+       ret = fec_enet_mdio_wait(fep);
+       if (ret)
                netdev_err(fep->netdev, "MDIO write timeout\n");
-               ret  = -ETIMEDOUT;
-       }
 
 out:
        pm_runtime_mark_last_busy(dev);
        if (suppress_preamble)
                fep->phy_speed |= BIT(7);
 
+       /* Clear MMFR to avoid to generate MII event by writing MSCR.
+        * MII event generation condition:
+        * - writing MSCR:
+        *      - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
+        *        mscr_reg_data_in[7:0] != 0
+        * - writing MMFR:
+        *      - mscr[7:0]_not_zero
+        */
+       writel(0, fep->hwp + FEC_MII_DATA);
+
        writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
+       /* Clear any pending transaction complete indication */
+       writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
+
        fep->mii_bus = mdiobus_alloc();
        if (fep->mii_bus == NULL) {
                err = -ENOMEM;
                fep->irq[i] = irq;
        }
 
-       init_completion(&fep->mdio_done);
        ret = fec_enet_mii_init(pdev);
        if (ret)
                goto failed_mii_init;